diff --git a/arch/arm/boot/dts/rk3036-pinctrl.dtsi b/arch/arm/boot/dts/rk3036-pinctrl.dtsi
index 55249f0a73c8..d5225b100b8a 100755
--- a/arch/arm/boot/dts/rk3036-pinctrl.dtsi
+++ b/arch/arm/boot/dts/rk3036-pinctrl.dtsi
@@ -415,6 +415,53 @@
 
 		};
 
+		gpio1_nandc {
+			nandc_ale:nandc-ale {
+				rockchip,pins = <NAND_ALE>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;
+			};
+
+			nandc_cle:nandc-cle {
+				rockchip,pins = <NAND_CLE>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;
+			};
+
+			nandc_wrn:nandc-wrn {
+				rockchip,pins = <NAND_WRN>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;
+			};
+
+			nandc_rdn:nandc-rdn {
+				rockchip,pins = <NAND_RDN>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;
+			};
+
+			nandc_rdy:nandc-rdy {
+				rockchip,pins = <NAND_RDY>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;
+			};
+
+			nandc_cs0:nandc-cs0 {
+				rockchip,pins = <NAND_CS0>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;
+			};
+
+
+			nandc_data: nandc-data {
+				rockchip,pins = <NAND_D0>,
+						<NAND_D1>,
+						<NAND_D2>,
+						<NAND_D3>,
+						<NAND_D4>,
+						<NAND_D5>,
+						<NAND_D6>,
+						<NAND_D7>;
+				rockchip,pull = <VALUE_PULL_DEFAULT>;	
+
+			};
+
+		};
+
 		gpio0_sdio0 {
 			sdio0_clk: sdio0_clk {
 				rockchip,pins = <MMC1_CLKOUT>;
diff --git a/arch/arm/boot/dts/rk3036-sdk.dts b/arch/arm/boot/dts/rk3036-sdk.dts
index d11cd215663d..52e4b1356b36 100755
--- a/arch/arm/boot/dts/rk3036-sdk.dts
+++ b/arch/arm/boot/dts/rk3036-sdk.dts
@@ -85,9 +85,13 @@
 };
 
 &nandc {
-	status = "disabled"; // used nand set "disabled" ,used emmc set "okay"
+	status = "okay"; // used nand set "okay" ,used emmc set "disabled"
 };  
 
+&nandc0reg {
+	status = "disabled"; // used nand set "disabled" ,used emmc set "okay"
+};
+
 &emmc {
 	clock-frequency = <100000000>;
 	clock-freq-min-max = <400000 100000000>;
diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index a074217b419b..e267b651b6bb 100755
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -103,10 +103,17 @@
 		compatible = "rockchip,rk-nandc";
 		reg = <0x10500000 0x4000>;
 		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+		//pinctrl-names = "default";
+		//pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
 		nandc_id = <0>;
 		clocks = <&clk_nandc>, <&clk_gates5 9>, <&clk_gates10 4>;
 		clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 	};
+	
+	nandc0reg: nandc0@10500000 {
+		compatible = "rockchip,rk-nandc";
+		reg = <0x10500000 0x4000>;
+	};
 
 	spi0: spi@20074000 {
 		compatible = "rockchip,rockchip-spi";