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drm: bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1

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There're an register define error in ANALOGIX_DP_PLL_REG_1 which introduced
by commit 45970584ea (FROMLIST: drm: bridge:
analogix/dp: add some rk3288 special registers setting).

The PHY PLL input clock source is selected by ANALOGIX_DP_PLL_REG_1
BIT 0, not BIT 1.

Change-Id: I8cb806d23144697225f626aaa2af19e6379dfe51
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
This commit is contained in:
Yakir Yang
2016-03-28 10:48:19 +08:00
committed by Gerrit Code Review
parent 7a8bd6a860
commit 455be1a2af
1 changed files with 2 additions and 2 deletions
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4
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
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@@ -163,8 +163,8 @@
#define HSYNC_POLARITY_CFG (0x1 << 0)
/* ANALOGIX_DP_PLL_REG_1 */
#define REF_CLK_24M (0x1 << 1)
#define REF_CLK_27M (0x0 << 1)
#define REF_CLK_24M (0x1 << 0)
#define REF_CLK_27M (0x0 << 0)
/* ANALOGIX_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)