From 45721e597612ddb7e94d3d983e2a9adcd90604c0 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Wed, 10 Oct 2018 17:48:43 +0800 Subject: [PATCH] clk: rockchip: rk1808: support npu half divider Change-Id: I78d8734b96e5982e2f0dcd08cf1747ff3d8f6e21 Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk1808.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk1808.c b/drivers/clk/rockchip/clk-rk1808.c index c810587e7490..47604a6b346c 100644 --- a/drivers/clk/rockchip/clk-rk1808.c +++ b/drivers/clk/rockchip/clk-rk1808.c @@ -334,9 +334,9 @@ static struct rockchip_clk_branch rk1808_clk_branches[] __initdata = { /* * Clock-Architecture Diagram 4 */ - COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_apll_p, 0, + COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_apll_p, 0, RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS), - COMPOSITE_NOGATE(0, "clk_npu_np5", mux_gpll_cpll_apll_p, 0, + COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_apll_p, 0, RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS), MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT, RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),