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lcd: add lcd_driver support for tm2 [2/2]

Browse Source 
PD#SWPL-6398

Problem:
add lcd_driver support

Solution:
add lcd_chip_tm2 and panel.dtsi

Verify:
ab301

Change-Id: I3cb5b67826ea2612e69b206168497771d5ced4b2
Signed-off-by: shaochan.liu <shaochan.liu@amlogic.com>

Conflicts:
	MAINTAINERS
	arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
	drivers/amlogic/media/vout/lcd/lcd_debug.c
	drivers/amlogic/media/vout/lcd/lcd_phy_config.c
	drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
	drivers/amlogic/media/vout/lcd/lcd_tcon.c
	drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
This commit is contained in:
shaochan.liu
2019-03-28 20:10:48 +08:00
committed by Dongjin Kim
parent 52398cc6ca
commit 45845922e5
20 changed files with 4058 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
MAINTAINERS
View File

@@ -14834,10 +14834,16 @@ M: Qianggui Song <qianggui.song@amlogic.com>
F: drivers/amlogic/pinctrl/pinctrl-meson-tm2.c
F: include/dt-bindings/gpio/meson-tm2-gpio.h
AMLOGIC MESON TM2 CLOCK DRIVER
M: Jian Hu <jian.hu@amlogic.com>
F: driver/amlogic/clk/tm2/*
AMLOGIC TL1 VAD
M: Wenbiao Zhang <wenbiao.zhang@amlogic.com>
F: include/linux/amlogic/vad_api.h
AMLOGIC MESON TM2 LCD DTS
M: Shaochan Liu <shaochan.liu@amlogic.com>
F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
F: arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi
F: arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
AMLOGIC SM1 S905X3 DTS
M: Xiaoliang Wang <xiaoliang.wang@amlogic.com>

1066
arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab301-panel.dtsi Normal file
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File diff suppressed because it is too large Load Diff

589
arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi Normal file
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@@ -0,0 +1,589 @@
/*
* arch/arm/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
*
* Copyright (C) 2016 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/ {
lcd {
compatible = "amlogic, lcd-tm2";
status = "okay";
mode = "tv";
fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */
key_valid = <0>;
clocks = <&clkc CLKID_VCLK2_ENCL
&clkc CLKID_VCLK2_VENCL
&clkc CLKID_TCON
&clkc CLKID_FCLK_DIV5
&clkc CLKID_TCON_PLL_COMP>;
clock-names = "encl_top_gate",
"encl_int_gate",
"tcon_gate",
"fclk_div5",
"clk_tcon";
reg = <0xff660000 0x8100
0xff634400 0x300>;
interrupts = <0 3 1
0 78 1
0 88 1>;
interrupt-names = "vsync","vbyone","tcon";
pinctrl-names = "vbyone","vbyone_off","tcon","tcon_off";
pinctrl-0 = <&lcd_vbyone_pins>;
pinctrl-1 = <&lcd_vbyone_off_pins>;
pinctrl-2 = <&lcd_tcon_pins>;
pinctrl-3 = <&lcd_tcon_off_pins>;
pinctrl_version = <2>; /* for uboot */
/* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */
/* power index:(gpios_index, or extern_index, 0xff=invalid) */
/* power value:(0=output low, 1=output high, 2=input) */
/* power delay:(unit in ms) */
lvds_0{
model_name = "1080p-vfreq";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
2060 2650 /*h_period_min,max*/
1100 1480 /*v_period_min,max*/
120000000 160000000>; /*pclk_min,max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0xf 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
lvds_1{
model_name = "1080p-hfreq_hdmi";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
2080 2720 /*h_period min, max*/
1100 1380 /*v_period min, max*/
133940000 156000000>; /*pclk_min, max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
4 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level */
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0xf 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
vbyone_0{
model_name = "public_2region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
2 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
vbyone_1{
model_name = "public_1region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2790 /*v_period_min, max*/
552000000 632000000>; /*pclk_min,max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
1 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_0{
model_name = "p2p_ceds";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
5000 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x0 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
12 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_1{
model_name = "p2p_ceds";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
5000 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x0 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_2{
model_name = "p2p_chpi";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x10 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_3{
model_name = "p2p_chpi";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x10 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
12 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
mlvds_0{
model_name = "mlvds_1080p";
interface = "minilvds"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
2080 2720 /*h_period_min, max*/
2200 1125 /*v_period_min, max*/
133940000 156000000>; /*pclk_min, max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
minilvds_attr = <
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0x660 /* clk_phase */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 0>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
mlvds_1{
model_name = "mlvds_768p";
interface = "minilvds";/*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
1366 768 /*h_active, v_active*/
1560 806 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
1460 2000 /*h_period_min, max*/
784 1015 /*v_period_min, max*/
50000000 85000000>; /*pclk_min, max*/
lcd_timing = <
56 64 0 /*hs_width, hs_bp, hs_pol*/
3 28 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
minilvds_attr = <
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0x660 /* clk_phase */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 0>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
};
lcd_extern{
compatible = "amlogic, lcd_extern";
status = "okay";
key_valid = <0>;
i2c_bus = "i2c_bus_1";
extern_0{
index = <0>;
extern_name = "ext_default";
status = "disabled";
type = <0>; /*0=i2c, 1=spi, 2=mipi*/
i2c_address = <0x1c>; /*7bit i2c_addr*/
i2c_address2 = <0xff>;
cmd_size = <0xff>; /*dynamic cmd_size*/
/* init on/off:
* fixed cmd_size: (type, value...);
* cmd_size include all data.
* dynamic cmd_size: (type, cmd_size, value...);
* cmd_size include value.
*/
/* type: 0x00=cmd with delay(bit[3:0]=1 for address2),
* 0xc0=cmd(bit[3:0]=1 for address2),
* 0xf0=gpio,
* 0xfd=delay,
* 0xff=ending
*/
/* value: i2c or spi cmd, or gpio index & level */
/* delay: unit ms */
init_on = <
0xc0 7 0x20 0x01 0x02 0x00 0x40 0xFF 0x00
0xc0 7 0x80 0x02 0x00 0x40 0x62 0x51 0x73
0xc0 7 0x61 0x06 0x00 0x00 0x00 0x00 0x00
0xc0 7 0xC1 0x05 0x0F 0x00 0x08 0x70 0x00
0xc0 7 0x13 0x01 0x00 0x00 0x00 0x00 0x00
0xc0 7 0x3D 0x02 0x01 0x00 0x00 0x00 0x00
0xc0 7 0xED 0x0D 0x01 0x00 0x00 0x00 0x00
0xc0 7 0x23 0x02 0x00 0x00 0x00 0x00 0x00
0xfd 1 10 /* delay 10ms */
0xff 0>; /*ending*/
init_off = <0xff 0>; /*ending*/
};
extern_1{
index = <1>;
extern_name = "i2c_T5800Q";
status = "disabled";
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
i2c_address = <0x1c>; /* 7bit i2c address */
};
extern_2{
index = <2>;
extern_name = "i2c_ANX6862_7911";
status = "okay";
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
i2c_address = <0x20>; /* 7bit i2c address */
i2c_address2 = <0x74>; /* 7bit i2c address */
cmd_size = <0xff>;
init_on = <
0xc0 2 0x01 0x2b
0xc0 2 0x02 0x05
0xc0 2 0x03 0x00
0xc0 2 0x04 0x00
0xc0 2 0x05 0x0c
0xc0 2 0x06 0x04
0xc0 2 0x07 0x21
0xc0 2 0x08 0x0f
0xc0 2 0x09 0x04
0xc0 2 0x0a 0x00
0xc0 2 0x0b 0x04
0xc0 2 0xff 0x00
0xfd 1 100 /* delay 100ms */
0xc1 2 0x01 0xca
0xc1 2 0x02 0x3b
0xc1 2 0x03 0x33
0xc1 2 0x04 0x05
0xc1 2 0x05 0x2c
0xc1 2 0x06 0xf2
0xc1 2 0x07 0x9c
0xc1 2 0x08 0x1b
0xc1 2 0x09 0x82
0xc1 2 0x0a 0x3d
0xc1 2 0x0b 0x20
0xc1 2 0x0c 0x11
0xc1 2 0x0d 0xc4
0xc1 2 0x0e 0x1a
0xc1 2 0x0f 0x31
0xc1 2 0x10 0x4c
0xc1 2 0x11 0x12
0xc1 2 0x12 0x90
0xc1 2 0x13 0xf7
0xc1 2 0x14 0x0c
0xc1 2 0x15 0x20
0xc1 2 0x16 0x13
0xff 0>; /*ending*/
init_off = <0xff 0>; /*ending*/
};
};
}; /* end of / */

5
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -19,6 +19,7 @@
#include "mesontm2.dtsi"
#include "partition_mbox_normal.dtsi"
#include "mesontm2_t962x3_ab301-panel.dtsi"
/ {
model = "Amlogic TM2 T962E2 AB301";
@@ -1894,6 +1895,10 @@
status = "okay";
};
&pwm_cd {
status = "okay";
};
&saradc {
status = "okay";
};

1
arch/arm/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -19,6 +19,7 @@
#include "mesontm2.dtsi"
#include "partition_mbox_normal.dtsi"
#include "mesontm2_t962x3_ab309-panel.dtsi"
/ {
model = "Amlogic TM2 T962X3 AB309";

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/*
* arch/arm64/boot/dts/amlogic/mesontm2_t962x3_ab309-panel.dtsi
*
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
/ {
lcd {
compatible = "amlogic, lcd-tm2";
status = "okay";
mode = "tv";
fr_auto_policy = <0>; /* 0=disable, 1=60/50hz, 2=60/50/48hz */
key_valid = <0>;
clocks = <&clkc CLKID_VCLK2_ENCL
&clkc CLKID_VCLK2_VENCL
&clkc CLKID_TCON
&clkc CLKID_FCLK_DIV5
&clkc CLKID_TCON_PLL_COMP>;
clock-names = "encl_top_gate",
"encl_int_gate",
"tcon_gate",
"fclk_div5",
"clk_tcon";
reg = <0x0 0xff660000 0x0 0x8100
0x0 0xff634400 0x0 0x300>;
interrupts = <0 3 1
0 78 1
0 88 1>;
interrupt-names = "vsync","vbyone","tcon";
pinctrl-names = "vbyone","vbyone_off","tcon","tcon_off";
pinctrl-0 = <&lcd_vbyone_pins>;
pinctrl-1 = <&lcd_vbyone_off_pins>;
pinctrl-2 = <&lcd_tcon_pins>;
pinctrl-3 = <&lcd_tcon_off_pins>;
pinctrl_version = <2>; /* for uboot */
/* power type:(0=cpu_gpio, 2=signal, 3=extern, 0xff=ending) */
/* power index:(gpios_index, or extern_index, 0xff=invalid) */
/* power value:(0=output low, 1=output high, 2=input) */
/* power delay:(unit in ms) */
lvds_0{
model_name = "1080p-vfreq";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
2060 2650 /*h_period_min,max*/
1100 1480 /*v_period_min,max*/
120000000 160000000>; /*pclk_min,max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0xf 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
lvds_1{
model_name = "1080p-hfreq_hdmi";
interface = "lvds"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
2080 2720 /*h_period min, max*/
1100 1380 /*v_period min, max*/
133940000 156000000>; /*pclk_min, max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
4 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level */
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
lvds_attr = <
1 /*lvds_repack*/
1 /*dual_port*/
0 /*pn_swap*/
0 /*port_swap*/
0>; /*lane_reverse*/
phy_attr=<0xf 0>; /*vswing_level, preem_level*/
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 0 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
vbyone_0{
model_name = "public_2region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
2 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable */
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
vbyone_1{
model_name = "public_1region";
interface = "vbyone"; /*lcd_interface(lvds, vbyone)*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
10 /*lcd_bits*/
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 4800 /*h_period_min, max*/
2200 2790 /*v_period_min, max*/
552000000 632000000>; /*pclk_min,max*/
lcd_timing = <
33 477 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
vbyone_attr = <
8 /*lane_count*/
1 /*region_num*/
4 /*byte_mode*/
4>; /*color_fmt*/
vbyone_intr_enable = <
1 /*vbyone_intr_enable*/
3>; /*vbyone_vsync_intr_enable*/
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_0{
model_name = "p2p_ceds";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
5000 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x0 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
12 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_1{
model_name = "p2p_ceds";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
5000 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x0 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_2{
model_name = "p2p_chpi";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x10 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
p2p_3{
model_name = "p2p_chpi";
interface = "p2p"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
3840 2160 /*h_active, v_active*/
4400 2250 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
4240 5100 /*h_period_min, max*/
2200 2760 /*v_period_min, max*/
480000000 624000000>; /*pclk_min, max*/
lcd_timing = <
16 29 0 /*hs_width, hs_bp, hs_pol*/
6 65 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
p2p_attr = <
0x10 /* p2p_teyp:
* 0x0=ceds, 0x1=cmpi, 0x2=isp, 0x3=epi,
* 0x10=chpi, 0x11=cspi, 0x12=usit
*/
12 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 1>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
mlvds_0{
model_name = "mlvds_1080p";
interface = "minilvds"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
1920 1080 /*h_active, v_active*/
2200 1125 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
2080 2720 /*h_period_min, max*/
2200 1125 /*v_period_min, max*/
133940000 156000000>; /*pclk_min, max*/
lcd_timing = <
44 148 0 /*hs_width, hs_bp, hs_pol*/
5 30 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
minilvds_attr = <
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0x660 /* clk_phase */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 0>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
mlvds_1{
model_name = "mlvds_768p";
interface = "minilvds"; /*lcd_interface
*(lvds, vbyone, minilvds, p2p)
*/
basic_setting = <
1366 768 /*h_active, v_active*/
1560 806 /*h_period, v_period*/
8 /*lcd_bits */
16 9>; /*screen_widht, screen_height*/
range_setting = <
1460 2000 /*h_period_min, max*/
784 1015 /*v_period_min, max*/
50000000 85000000>; /*pclk_min, max*/
lcd_timing = <
56 64 0 /*hs_width, hs_bp, hs_pol*/
3 28 0>; /*vs_width, vs_bp, vs_pol*/
clk_attr = <
2 /*fr_adj_type
*(0=clk, 1=htotal, 2=vtotal, 3=auto_range,
* 4=hdmi_mode)
*/
0 /*clk_ss_level*/
1 /*clk_auto_generate*/
0>; /*pixel_clk(unit in Hz)*/
minilvds_attr = <
6 /* channel_num */
0x76543210 /* channel_sel0 */
0xba98 /* channel_sel1 */
0x660 /* clk_phase */
0 /* pn_swap */
0>; /* bit_swap */
phy_attr=<0xf 0>; /* vswing_level, preem_level */
/* power step: type, index, value, delay(ms) */
power_on_step = <
2 0 0 10 /*signal enable*/
0xff 0 0 0>; /*ending*/
power_off_step = <
2 0 0 10 /*signal disable*/
0xff 0 0 0>; /*ending*/
backlight_index = <0xff>;
};
};
lcd_extern{
compatible = "amlogic, lcd_extern";
status = "okay";
key_valid = <0>;
i2c_bus = "i2c_bus_1";
extern_0{
index = <0>;
extern_name = "ext_default";
status = "disabled";
type = <0>; /*0=i2c, 1=spi, 2=mipi*/
i2c_address = <0x1c>; /*7bit i2c_addr*/
i2c_address2 = <0xff>;
cmd_size = <0xff>; /*dynamic cmd_size*/
/* init on/off:
* fixed cmd_size: (type, value...);
* cmd_size include all data.
* dynamic cmd_size: (type, cmd_size, value...);
* cmd_size include value.
*/
/* type: 0x00=cmd with delay(bit[3:0]=1 for address2),
* 0xc0=cmd(bit[3:0]=1 for address2),
* 0xf0=gpio,
* 0xfd=delay,
* 0xff=ending
*/
/* value: i2c or spi cmd, or gpio index & level */
/* delay: unit ms */
init_on = <
0xc0 7 0x20 0x01 0x02 0x00 0x40 0xFF 0x00
0xc0 7 0x80 0x02 0x00 0x40 0x62 0x51 0x73
0xc0 7 0x61 0x06 0x00 0x00 0x00 0x00 0x00
0xc0 7 0xC1 0x05 0x0F 0x00 0x08 0x70 0x00
0xc0 7 0x13 0x01 0x00 0x00 0x00 0x00 0x00
0xc0 7 0x3D 0x02 0x01 0x00 0x00 0x00 0x00
0xc0 7 0xED 0x0D 0x01 0x00 0x00 0x00 0x00
0xc0 7 0x23 0x02 0x00 0x00 0x00 0x00 0x00
0xfd 1 10 /* delay 10ms */
0xff 0>; /*ending*/
init_off = <0xff 0>; /*ending*/
};
extern_1{
index = <1>;
extern_name = "i2c_T5800Q";
status = "disabled";
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
i2c_address = <0x1c>; /* 7bit i2c address */
};
extern_2{
index = <2>;
extern_name = "i2c_ANX6862_7911";
status = "okay";
type = <0>; /* 0=i2c, 1=spi, 2=mipi */
i2c_address = <0x20>; /* 7bit i2c address */
i2c_address2 = <0x74>; /* 7bit i2c address */
cmd_size = <0xff>;
init_on = <
0xc0 2 0x01 0x2b
0xc0 2 0x02 0x05
0xc0 2 0x03 0x00
0xc0 2 0x04 0x00
0xc0 2 0x05 0x0c
0xc0 2 0x06 0x04
0xc0 2 0x07 0x21
0xc0 2 0x08 0x0f
0xc0 2 0x09 0x04
0xc0 2 0x0a 0x00
0xc0 2 0x0b 0x04
0xc0 2 0xff 0x00
0xfd 1 100 /* delay 100ms */
0xc1 2 0x01 0xca
0xc1 2 0x02 0x3b
0xc1 2 0x03 0x33
0xc1 2 0x04 0x05
0xc1 2 0x05 0x2c
0xc1 2 0x06 0xf2
0xc1 2 0x07 0x9c
0xc1 2 0x08 0x1b
0xc1 2 0x09 0x82
0xc1 2 0x0a 0x3d
0xc1 2 0x0b 0x20
0xc1 2 0x0c 0x11
0xc1 2 0x0d 0xc4
0xc1 2 0x0e 0x1a
0xc1 2 0x0f 0x31
0xc1 2 0x10 0x4c
0xc1 2 0x11 0x12
0xc1 2 0x12 0x90
0xc1 2 0x13 0xf7
0xc1 2 0x14 0x0c
0xc1 2 0x15 0x20
0xc1 2 0x16 0x13
0xff 0>; /*ending*/
init_off = <0xff 0>; /*ending*/
};
};
}; /* end of / */

22
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -19,6 +19,7 @@
#include "mesontm2.dtsi"
#include "partition_mbox_normal.dtsi"
#include "mesontm2_t962x3_ab301-panel.dtsi"
/ {
model = "Amlogic TM2 T962E2 AB301";
@@ -92,6 +93,14 @@
linux,contiguous-region;
};
lcd_tcon_reserved:linux,lcd_tcon {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0xc00000>;
alignment = <0x0 0x400000>;
alloc-ranges = <0x0 0x7ec00000 0x0 0xc00000>;
};
/* codec shared reserved */
codec_mm_reserved:linux,codec_mm_reserved {
compatible = "amlogic, codec-mm-reserved";
@@ -1659,6 +1668,15 @@
output-low;
};
};
}; /* end of pinctrl_periphs */
&pinctrl_aobus {
spdifout: spdifout {
mux { /* gpiao_10 */
groups = "spdif_out_ao";
function = "spdif_out_ao";
};
};
}; /* end of pinctrl_periphs */
@@ -1854,6 +1872,10 @@
status = "okay";
};
&pwm_cd {
status = "okay";
};
&saradc {
status = "okay";
};

3
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab309.dts
View File

@@ -19,9 +19,10 @@
#include "mesontm2.dtsi"
#include "partition_mbox_normal.dtsi"
#include "mesontm2_t962x3_ab309-panel.dtsi"
/ {
model = "Amlogic TM2 T962E2 AB319";
model = "Amlogic TM2 T962X3 AB309";
amlogic-dt-id = "tm2_t962x3_ab309";
compatible = "amlogic, tm2_t962x3_ab309";

10
drivers/amlogic/media/vout/backlight/aml_bl.c
View File

@@ -3376,6 +3376,12 @@ static struct bl_data_s bl_data_sm1 = {
.pwm_reg = pwm_reg_txlx,
};
static struct bl_data_s bl_data_tm2 = {
.chip_type = BL_CHIP_TM2,
.chip_name = "tm2",
.pwm_reg = pwm_reg_txlx,
};
static const struct of_device_id bl_dt_match_table[] = {
{
.compatible = "amlogic, backlight-gxl",
@@ -3413,6 +3419,10 @@ static const struct of_device_id bl_dt_match_table[] = {
.compatible = "amlogic, backlight-sm1",
.data = &bl_data_sm1,
},
{
.compatible = "amlogic, backlight-tm2",
.data = &bl_data_tm2,
},
{},
};
#endif

1
drivers/amlogic/media/vout/backlight/aml_ldim/ldim_drv.c
View File

@@ -3013,6 +3013,7 @@ int aml_ldim_probe(struct platform_device *pdev)
/* ldim_op_func */
switch (bl_drv->data->chip_type) {
case BL_CHIP_TL1:
case BL_CHIP_TM2:
devp->ldim_op_func = &ldim_op_func_tl1;
break;
case BL_CHIP_TXLX:

1
drivers/amlogic/media/vout/lcd/lcd_clk_config.c
View File

@@ -2871,6 +2871,7 @@ static void lcd_clk_config_chip_init(struct lcd_clk_config_s *cConf)
cConf->data = &lcd_clk_data_g12b_path0;
break;
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
cConf->data = &lcd_clk_data_tl1;
break;
default:

30
drivers/amlogic/media/vout/lcd/lcd_debug.c
View File

@@ -597,6 +597,35 @@ static int lcd_info_print(char *buf, int offset)
return len;
}
static void lcd_reg_print_serializer(char *buf, int offset)
{
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int reg0, reg1;
int n, len = 0;
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
reg0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
default:
reg0 = HHI_LVDS_TX_PHY_CNTL0;
reg1 = HHI_LVDS_TX_PHY_CNTL1;
break;
}
n = lcd_debug_info_len(len + offset);
len += snprintf((buf+len), n, "\nserializer regs:\n");
n = lcd_debug_info_len(len + offset);
len += snprintf((buf+len), n,
"HHI_LVDS_TX_PHY_CNTL0 [0x%04x] = 0x%08x\n",
reg0, lcd_hiu_read(reg0));
len += snprintf((buf+len), n,
"HHI_LVDS_TX_PHY_CNTL1 [0x%04x] = 0x%08x\n",
reg1, lcd_hiu_read(reg1));
}
static int lcd_reg_print_ttl(char *buf, int offset)
{
unsigned int reg;
@@ -4464,6 +4493,7 @@ int lcd_debug_probe(void)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_debug_info_reg = &lcd_debug_info_reg_tl1;
lcd_debug_info_if_lvds.reg_dump_phy =
lcd_reg_print_phy_analog_tl1;

566
drivers/amlogic/media/vout/lcd/lcd_phy_config.c Normal file
View File

@@ -0,0 +1,566 @@
/*
* drivers/amlogic/media/vout/lcd/lcd_phy_config.c
*
* Copyright (C) 2017 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/init.h>
#include <linux/version.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/amlogic/media/vout/lcd/lcd_vout.h>
#include "lcd_reg.h"
#include "lcd_phy_config.h"
#include "lcd_common.h"
static unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf)
{
unsigned int channel_on = 0;
if (pconf->lcd_control.lvds_config->dual_port == 0) {
if (pconf->lcd_control.lvds_config->lane_reverse == 0) {
switch (pconf->lcd_basic.lcd_bits) {
case 6:
channel_on = 0xf;
break;
case 8:
channel_on = 0x1f;
break;
case 10:
default:
channel_on = 0x3f;
break;
}
} else {
switch (pconf->lcd_basic.lcd_bits) {
case 6:
channel_on = 0x3c;
break;
case 8:
channel_on = 0x3e;
break;
case 10:
default:
channel_on = 0x3f;
break;
}
}
if (pconf->lcd_control.lvds_config->port_swap == 1)
channel_on = (channel_on << 6); /* use channel B */
} else {
if (pconf->lcd_control.lvds_config->lane_reverse == 0) {
switch (pconf->lcd_basic.lcd_bits) {
case 6:
channel_on = 0x3cf;
break;
case 8:
channel_on = 0x7df;
break;
case 10:
default:
channel_on = 0xfff;
break;
}
} else {
switch (pconf->lcd_basic.lcd_bits) {
case 6:
channel_on = 0xf3c;
break;
case 8:
channel_on = 0xfbe;
break;
case 10:
default:
channel_on = 0xfff;
break;
}
}
}
return channel_on;
}
void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
{
unsigned int vswing, preem, clk_vswing, clk_preem, channel_on;
unsigned int data32, size;
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
struct lvds_config_s *lvds_conf;
if (lcd_debug_print_flag)
LCDPR("%s: %d\n", __func__, status);
lvds_conf = pconf->lcd_control.lvds_config;
if (status) {
vswing = lvds_conf->phy_vswing & 0xf;
preem = lvds_conf->phy_preem & 0xf;
clk_vswing = lvds_conf->phy_clk_vswing & 0xf;
clk_preem = lvds_conf->phy_clk_preem & 0xf;
if (lcd_debug_print_flag)
LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem);
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
sizeof(unsigned int);
if (preem >= size) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = 0;
}
data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
0xff2027e0 | vswing);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
break;
default:
if (vswing > 7) {
LCDERR("%s: invalid vswing=0x%x, use default\n",
__func__, vswing);
vswing = LVDS_PHY_VSWING_DFT;
}
if (preem > 7) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = LVDS_PHY_PREEM_DFT;
}
if (clk_vswing > 3) {
LCDERR(
"%s: invalid clk_vswing=0x%x, use default\n",
__func__, clk_vswing);
clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
}
if (clk_preem > 7) {
LCDERR(
"%s: invalid clk_preem=0x%x, use default\n",
__func__, clk_preem);
clk_preem = LVDS_PHY_CLK_PREEM_DFT;
}
channel_on = lcd_lvds_channel_on_value(pconf);
data32 = LVDS_PHY_CNTL1_G9TV |
(vswing << 26) | (preem << 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = LVDS_PHY_CNTL2_G9TV;
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = LVDS_PHY_CNTL3_G9TV |
(channel_on << 16) |
(clk_vswing << 8) |
(clk_preem << 5);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
break;
}
} else {
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
break;
default:
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
break;
}
}
}
void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
{
unsigned int vswing, preem, ext_pullup;
unsigned int data32, size;
unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4};
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
struct vbyone_config_s *vbyone_conf;
if (lcd_debug_print_flag)
LCDPR("%s: %d\n", __func__, status);
vbyone_conf = pconf->lcd_control.vbyone_config;
if (status) {
ext_pullup = (vbyone_conf->phy_vswing >> 4) & 0x3;
vswing = vbyone_conf->phy_vswing & 0xf;
preem = vbyone_conf->phy_preem & 0xf;
if (lcd_debug_print_flag) {
LCDPR("vswing=0x%x, prrem=0x%x\n",
vbyone_conf->phy_vswing, preem);
}
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
sizeof(unsigned int);
if (preem >= size) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = 0x1;
}
data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
if (ext_pullup) {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
0xff2027e0 | vswing);
} else {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
0xf02027a0 | vswing);
}
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
break;
default:
if (vswing > 7) {
LCDERR("%s: invalid vswing=0x%x, use default\n",
__func__, vswing);
vswing = VX1_PHY_VSWING_DFT;
}
if (preem > 7) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = VX1_PHY_PREEM_DFT;
}
if (ext_pullup) {
data32 = VX1_PHY_CNTL1_G9TV_PULLUP |
(vswing << 3);
} else {
data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3);
}
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) |
(rinner_table[ext_pullup] << 8);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
data32 = VX1_PHY_CNTL3_G9TV;
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
break;
}
} else {
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
break;
default:
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
break;
}
}
}
void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
{
unsigned int vswing, preem;
unsigned int data32, size, cntl16;
struct mlvds_config_s *mlvds_conf;
if (lcd_debug_print_flag)
LCDPR("%s: %d\n", __func__, status);
mlvds_conf = pconf->lcd_control.mlvds_config;
if (status) {
vswing = mlvds_conf->phy_vswing & 0xf;
preem = mlvds_conf->phy_preem & 0xf;
if (lcd_debug_print_flag)
LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem);
size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
sizeof(unsigned int);
if (preem >= size) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = 0;
}
data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
0xff2027e0 | vswing);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
cntl16 = (mlvds_conf->pi_clk_sel << 12);
cntl16 |= 0x80000000;
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
} else {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
}
}
void lcd_p2p_phy_set(struct lcd_config_s *pconf, int status)
{
unsigned int vswing, preem;
unsigned int data32, size, cntl16;
struct p2p_config_s *p2p_conf;
if (lcd_debug_print_flag)
LCDPR("%s: %d\n", __func__, status);
p2p_conf = pconf->lcd_control.p2p_config;
if (status) {
vswing = p2p_conf->phy_vswing & 0xf;
preem = p2p_conf->phy_preem & 0xf;
if (lcd_debug_print_flag)
LCDPR("vswing=0x%x, prrem=0x%x\n", vswing, preem);
switch (p2p_conf->p2p_type) {
case P2P_CEDS:
case P2P_CMPI:
case P2P_ISP:
case P2P_EPI:
size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
sizeof(unsigned int);
if (preem >= size) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = 0x1;
}
data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14,
0xff2027a0 | vswing);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0x80000000);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
break;
case P2P_CHPI: /* low common mode */
case P2P_CSPI:
case P2P_USIT:
size = sizeof(p2p_low_common_phy_preem_tl1) /
sizeof(unsigned int);
if (preem >= size) {
LCDERR("%s: invalid preem=0x%x, use default\n",
__func__, preem);
preem = 0x1;
}
data32 = p2p_low_common_phy_preem_tl1[preem];
cntl16 = 0x80000000;
if (p2p_conf->p2p_type == P2P_CHPI) {
/* weakly pull down */
data32 &= ~((1 << 19) | (1 << 3));
}
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0xfe60027f);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, data32);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0x40004);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, data32);
break;
default:
LCDERR("%s: invalid p2p_type %d\n",
__func__, p2p_conf->p2p_type);
break;
}
} else {
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL14, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL15, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL16, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL8, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL9, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL10, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL11, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL4, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL12, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL6, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL13, 0);
lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL7, 0);
}
}
void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status)
{
unsigned int phy_reg, phy_bit, phy_width;
unsigned int lane_cnt;
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
if (status) {
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_G12A:
case LCD_CHIP_G12B:
case LCD_CHIP_SM1:
/* HHI_MIPI_CNTL0 */
/* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
lcd_hiu_write(HHI_MIPI_CNTL0,
(0xa487 << 16) | (0x8 << 0));
/* HHI_MIPI_CNTL1 */
/* DIF_REF_CTL2:15-0bit; bandgap bit16 */
lcd_hiu_write(HHI_MIPI_CNTL1,
(0x1 << 16) | (0x002e << 0));
/* HHI_MIPI_CNTL2 */
/* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */
lcd_hiu_write(HHI_MIPI_CNTL2,
(0x2680 << 16) | (0x45a << 0));
break;
default: /* LCD_CHIP_AXG */
/* HHI_MIPI_CNTL0 */
/* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
lcd_hiu_setb(HHI_MIPI_CNTL0, 0x1b8, 16, 10);
lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 26, 1); /* bandgap */
lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 29, 1); /* current */
lcd_hiu_setb(HHI_MIPI_CNTL0, 1, 31, 1);
lcd_hiu_setb(HHI_MIPI_CNTL0, 0x8, 0, 16);
/* HHI_MIPI_CNTL1 */
/* DIF_REF_CTL2:15-0bit */
lcd_hiu_write(HHI_MIPI_CNTL1, (0x001e << 0));
/* HHI_MIPI_CNTL2 */
/* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */
lcd_hiu_write(HHI_MIPI_CNTL2,
(0x26e0 << 16) | (0x459 << 0));
break;
}
phy_reg = HHI_MIPI_CNTL2;
phy_bit = MIPI_PHY_LANE_BIT;
phy_width = MIPI_PHY_LANE_WIDTH;
switch (pconf->lcd_control.mipi_config->lane_num) {
case 1:
lane_cnt = DSI_LANE_COUNT_1;
break;
case 2:
lane_cnt = DSI_LANE_COUNT_2;
break;
case 3:
lane_cnt = DSI_LANE_COUNT_3;
break;
case 4:
lane_cnt = DSI_LANE_COUNT_4;
break;
default:
lane_cnt = 0;
break;
}
lcd_hiu_setb(phy_reg, lane_cnt, phy_bit, phy_width);
} else {
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_G12A:
case LCD_CHIP_G12B:
case LCD_CHIP_SM1:
lcd_hiu_write(HHI_MIPI_CNTL0, 0);
lcd_hiu_write(HHI_MIPI_CNTL1, 0);
lcd_hiu_write(HHI_MIPI_CNTL2, 0);
break;
default:/* LCD_CHIP_AXG */
lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 16, 10);
lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 31, 1);
lcd_hiu_setb(HHI_MIPI_CNTL0, 0, 0, 16);
lcd_hiu_write(HHI_MIPI_CNTL1, 0x6);
lcd_hiu_write(HHI_MIPI_CNTL2, 0x00200000);
break;
}
}
}

84
drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
View File

@@ -376,7 +376,9 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
lcd_vcbus_write(ENCL_INBUF_CNTL1, (1 << 14) | (h_active - 1));
case LCD_CHIP_TM2:
/*[15:14]: 2'b10 or 2'b01*/
lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1));
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
break;
default:
@@ -412,6 +414,19 @@ static void lcd_ttl_control_set(struct lcd_config_s *pconf)
static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
{
unsigned int phy_div;
unsigned int reg_cntl0, reg_cntl1;
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
default:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
break;
}
if (pconf->lcd_control.lvds_config->dual_port)
phy_div = 2;
@@ -421,7 +436,15 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
/* set fifo_clk_sel: div 7 */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
/* set cntl_ser_en: 8-channel to 1 */
lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
break;
default:
break;
}
/* decoupling fifo enable, gated clock enable */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
@@ -482,10 +505,18 @@ static void lcd_lvds_control_set(struct lcd_config_s *pconf)
(1 << 12) | /* g_select //0:R, 1:G, 2:B, 3:0 */
(2 << 14)); /* b_select //0:R, 1:G, 2:B, 3:0 */
lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
if (lane_reverse)
lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_vcbus_write(P2P_CH_SWAP0, 0x76543210);
lcd_vcbus_write(P2P_CH_SWAP1, 0xba98);
break;
default:
lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
if (lane_reverse)
lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
break;
}
lcd_vcbus_write(LVDS_GEN_CNTL,
(lcd_vcbus_read(LVDS_GEN_CNTL) |
@@ -512,6 +543,20 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
{
unsigned int lcd_bits;
unsigned int div_sel, phy_div;
struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
unsigned int reg_cntl0, reg_cntl1;
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
default:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1;
break;
}
phy_div = pconf->lcd_control.vbyone_config->phy_div;
lcd_bits = pconf->lcd_basic.lcd_bits;
@@ -533,7 +578,15 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
/* set fifo_clk_sel */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
/* set cntl_ser_en: 8-channel to 1 */
lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
break;
default:
break;
}
/* decoupling fifo enable, gated clock enable */
lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
@@ -726,7 +779,22 @@ static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
/* lcd_vcbus_setb(LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order */
/* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);
/*lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);*/
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L, 0xff);
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H, 0x0);
lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 8, 4);
lcd_vcbus_setb(VBO_INSGN_CTRL, 0x7, 12, 4);
break;
default:
lcd_vcbus_write(VBO_INFILTER_CTRL, 0xff77);
break;
}
lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 2);
lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);
/*force vencl clk enable, otherwise, it might auto turn off by mipi DSI

2
drivers/amlogic/media/vout/lcd/lcd_tcon.c
View File

@@ -649,7 +649,7 @@ int lcd_tcon_probe(struct aml_lcd_drv_s *lcd_drv)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
lcd_tcon_data = &tcon_data_tl1;
case LCD_CHIP_TM2:
switch (lcd_drv->lcd_config->lcd_basic.lcd_type) {
case LCD_MLVDS:
case LCD_P2P:

19
drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
View File

@@ -379,7 +379,9 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
lcd_vcbus_write(ENCL_INBUF_CNTL1, (1 << 14) | (h_active - 1));
case LCD_CHIP_TM2:
/*[15:14]: 2'b10 or 2'b01*/
lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1));
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
break;
default:
@@ -407,6 +409,7 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
@@ -427,6 +430,7 @@ static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
break;
default:
@@ -496,12 +500,9 @@ static void lcd_lvds_control_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
ch_swap0 = 0x3210;
ch_swap1 = 0x7654;
ch_swap2 = 0xba98;
lcd_vcbus_write(LVDS_CH_SWAP0, ch_swap0);
lcd_vcbus_write(LVDS_CH_SWAP1, ch_swap1);
lcd_vcbus_write(LVDS_CH_SWAP2, ch_swap2);
case LCD_CHIP_TM2:
lcd_vcbus_write(P2P_CH_SWAP0, 0x76543210);
lcd_vcbus_write(P2P_CH_SWAP1, 0xba98);
break;
default:
lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
@@ -635,6 +636,7 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;
@@ -667,6 +669,7 @@ static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
lcd_hiu_setb(reg_cntl0, 0xfff, 16, 12);
switch (lcd_drv->data->chip_type) { /* pn swap */
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
lcd_hiu_setb(reg_cntl0, 1, 2, 1);
break;
default:
@@ -766,6 +769,7 @@ static void lcd_vbyone_hw_filter(int flag)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
if (flag) {
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L, 0xffff);
lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H, 0xf);
@@ -1450,6 +1454,7 @@ static void lcd_p2p_control_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
reg_cntl0 = HHI_LVDS_TX_PHY_CNTL0_TL1;
reg_cntl1 = HHI_LVDS_TX_PHY_CNTL1_TL1;
break;

10
drivers/amlogic/media/vout/lcd/lcd_vout.c
View File

@@ -1371,6 +1371,12 @@ static struct lcd_data_s lcd_data_sm1 = {
.reg_map_table = &lcd_reg_axg[0],
};
static struct lcd_data_s lcd_data_tm2 = {
.chip_type = LCD_CHIP_TM2,
.chip_name = "tm2",
.reg_map_table = &lcd_reg_tl1[0],
};
static const struct of_device_id lcd_dt_match_table[] = {
{
.compatible = "amlogic, lcd-gxl",
@@ -1408,6 +1414,10 @@ static const struct of_device_id lcd_dt_match_table[] = {
.compatible = "amlogic, lcd-sm1",
.data = &lcd_data_sm1,
},
{
.compatible = "amlogic, lcd-tm2",
.data = &lcd_data_tm2,
},
{},
};
#endif

1
include/linux/amlogic/media/vout/lcd/aml_bl.h
View File

@@ -51,6 +51,7 @@ enum bl_chip_type_e {
BL_CHIP_G12B,
BL_CHIP_TL1,
BL_CHIP_SM1,
BL_CHIP_TM2,
BL_CHIP_MAX,
};

1
include/linux/amlogic/media/vout/lcd/lcd_vout.h
View File

@@ -93,6 +93,7 @@ enum lcd_chip_e {
LCD_CHIP_G12B, /* 6 */
LCD_CHIP_TL1, /* 7 */
LCD_CHIP_SM1, /* 8 */
LCD_CHIP_TM2, /* 9 */
LCD_CHIP_MAX,
};