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iommu/vt-d: Fix to flush cache of PASID directory table

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[ Upstream commit 8a3b8e63f8 ]

Even the PCI devices don't support pasid capability, PASID table is
mandatory for a PCI device in scalable mode. However flushing cache
of pasid directory table for these devices are not taken after pasid
table is allocated as the "size" of table is zero. Fix it by
calculating the size by page order.

Found this when reading the code, no real problem encountered for now.

Fixes: 194b3348bd ("iommu/vt-d: Fix PASID directory pointer coherency")
Suggested-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Yanfei Xu <yanfei.xu@intel.com>
Link: https://lore.kernel.org/r/20230616081045.721873-1-yanfei.xu@intel.com
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Yanfei Xu
2023-08-09 20:48:04 +08:00
committed by Greg Kroah-Hartman
parent d9c47d2bf3
commit 45e3181d79
1 changed files with 1 additions and 1 deletions
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2
drivers/iommu/intel/pasid.c
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@@ -127,7 +127,7 @@ int intel_pasid_alloc_table(struct device *dev)
info->pasid_table = pasid_table;
if (!ecap_coherent(info->iommu->ecap))
clflush_cache_range(pasid_table->table, size);
clflush_cache_range(pasid_table->table, (1 << order) * PAGE_SIZE);
return 0;
}