mirror of
https://github.com/hardkernel/linux.git
synced 2026-06-07 19:30:30 +09:00
Merge tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drm
Pull drm updates from Dave Airlie:
"The drm core grew a new generic gpu virtual address manager, and new
execution locking helpers. These are used by nouveau now to provide
uAPI support for the userspace Vulkan driver. AMD had a bunch of new
IP core support, loads of refactoring around fbdev, but mostly just
the usual amount of stuff across the board.
core:
- fix gfp flags in drmm_kmalloc
gpuva:
- add new generic GPU VA manager (for nouveau initially)
syncobj:
- add new DRM_IOCTL_SYNCOBJ_EVENTFD ioctl
dma-buf:
- acquire resv lock for mmap() in exporters
- support dma-buf self import automatically
- docs fixes
backlight:
- fix fbdev interactions
atomic:
- improve logging
prime:
- remove struct gem_prim_mmap plus driver updates
gem:
- drm_exec: add locking over multiple GEM objects
- fix lockdep checking
fbdev:
- make fbdev userspace interfaces optional
- use linux device instead of fbdev device
- use deferred i/o helper macros in various drivers
- Make FB core selectable without drivers
- Remove obsolete flags FBINFO_DEFAULT and FBINFO_FLAG_DEFAULT
- Add helper macros and Kconfig tokens for DMA-allocated framebuffer
ttm:
- support init_on_free
- swapout fixes
panel:
- panel-edp: Support AUO B116XAB01.4
- Support Visionox R66451 plus DT bindings
- ld9040:
- Backlight support
- magic improved
- Kconfig fix
- Convert to of_device_get_match_data()
- Fix Kconfig dependencies
- simple:
- Set bpc value to fix warning
- Set connector type for AUO T215HVN01
- Support Innolux G156HCE-L01 plus DT bindings
- ili9881: Support TDO TL050HDV35 LCD panel plus DT bindings
- startek: Support KD070FHFID015 MIPI-DSI panel plus DT bindings
- sitronix-st7789v:
- Support Inanbo T28CP45TN89 plus DT bindings
- Support EDT ET028013DMA plus DT bindings
- Various cleanups
- edp: Add timings for N140HCA-EAC
- Allow panels and touchscreens to power sequence together
- Fix Innolux G156HCE-L01 LVDS clock
bridge:
- debugfs for chains support
- dw-hdmi:
- Improve support for YUV420 bus format
- CEC suspend/resume
- update EDID on HDMI detect
- dw-mipi-dsi: Fix enable/disable of DSI controller
- lt9611uxc: Use MODULE_FIRMWARE()
- ps8640: Remove broken EDID code
- samsung-dsim: Fix command transfer
- tc358764:
- Handle HS/VS polarity
- Use BIT() macro
- Various cleanups
- adv7511: Fix low refresh rate
- anx7625:
- Switch to macros instead of hardcoded values
- locking fixes
- tc358767: fix hardware delays
- sitronix-st7789v:
- Support panel orientation
- Support rotation property
- Add support for Jasonic JT240MHQS-HWT-EK-E3 plus DT bindings
amdgpu:
- SDMA 6.1.0 support
- HDP 6.1 support
- SMUIO 14.0 support
- PSP 14.0 support
- IH 6.1 support
- Lots of checkpatch cleanups
- GFX 9.4.3 updates
- Add USB PD and IFWI flashing documentation
- GPUVM updates
- RAS fixes
- DRR fixes
- FAMS fixes
- Virtual display fixes
- Soft IH fixes
- SMU13 fixes
- Rework PSP firmware loading for other IPs
- Kernel doc fixes
- DCN 3.0.1 fixes
- LTTPR fixes
- DP MST fixes
- DCN 3.1.6 fixes
- SMU 13.x fixes
- PSP 13.x fixes
- SubVP fixes
- GC 9.4.3 fixes
- Display bandwidth calculation fixes
- VCN4 secure submission fixes
- Allow building DC on RISC-V
- Add visible FB info to bo_print_info
- HBR3 fixes
- GFX9 MCBP fix
- GMC10 vmhub index fix
- GMC11 vmhub index fix
- Create a new doorbell manager
- SR-IOV fixes
- initial freesync panel replay support
- revert zpos properly until igt regression is fixeed
- use TTM to manage doorbell BAR
- Expose both current and average power via hwmon if supported
amdkfd:
- Cleanup CRIU dma-buf handling
- Use KIQ to unmap HIQ
- GFX 9.4.3 debugger updates
- GFX 9.4.2 debugger fixes
- Enable cooperative groups fof gfx11
- SVM fixes
- Convert older APUs to use dGPU path like newer APUs
- Drop IOMMUv2 path as it is no longer used
- TBA fix for aldebaran
i915:
- ICL+ DSI modeset sequence
- HDCP improvements
- MTL display fixes and cleanups
- HSW/BDW PSR1 restored
- Init DDI ports in VBT order
- General display refactors
- Start using plane scale factor for relative data rate
- Use shmem for dpt objects
- Expose RPS thresholds in sysfs
- Apply GuC SLPC min frequency softlimit correctly
- Extend Wa_14015795083 to TGL, RKL, DG1 and ADL
- Fix a VMA UAF for multi-gt platform
- Do not use stolen on MTL due to HW bug
- Check HuC and GuC version compatibility on MTL
- avoid infinite GPU waits due to premature release of request memory
- Fixes and updates for GSC memory allocation
- Display SDVO fixes
- Take stolen handling out of FBC code
- Make i915_coherent_map_type GT-centric
- Simplify shmem_create_from_object map_type
msm:
- SM6125 MDSS support
- DPU: SM6125 DPU support
- DSI: runtime PM support, burst mode support
- DSI PHY: SM6125 support in 14nm DSI PHY driver
- GPU: prepare for a7xx
- fix a690 firmware
- disable relocs on a6xx and newer
radeon:
- Lots of checkpatch cleanups
ast:
- improve device-model detection
- Represent BMV as virtual connector
- Report DP connection status
nouveau:
- add new exec/bind interface to support Vulkan
- document some getparam ioctls
- improve VRAM detection
- various fixes/cleanups
- workraound DPCD issues
ivpu:
- MMU updates
- debugfs support
- Support vpu4
virtio:
- add sync object support
atmel-hlcdc:
- Support inverted pixclock polarity
etnaviv:
- runtime PM cleanups
- hang handling fixes
exynos:
- use fbdev DMA helpers
- fix possible NULL ptr dereference
komeda:
- always attach encoder
omapdrm:
- use fbdev DMA helpers
ingenic:
- kconfig regmap fixes
loongson:
- support display controller
mediatek:
- Small mtk-dpi cleanups
- DisplayPort: support eDP and aux-bus
- Fix coverity issues
- Fix potential memory leak if vmap() fail
mgag200:
- minor fixes
mxsfb:
- support disabling overlay planes
panfrost:
- fix sync in IRQ handling
ssd130x:
- Support per-controller default resolution plus DT bindings
- Reduce memory-allocation overhead
- Improve intermediate buffer size computation
- Fix allocation of temporary buffers
- Fix pitch computation
- Fix shadow plane allocation
tegra:
- use fbdev DMA helpers
- Convert to devm_platform_ioremap_resource()
- support bridge/connector
- enable PM
tidss:
- Support TI AM625 plus DT bindings
- Implement new connector model plus driver updates
vkms:
- improve write back support
- docs fixes
- support gamma LUT
zynqmp-dpsub:
- misc fixes"
* tag 'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drm: (1327 commits)
drm/gpuva_mgr: remove unused prev pointer in __drm_gpuva_sm_map()
drm/tests/drm_kunit_helpers: Place correct function name in the comment header
drm/nouveau: uapi: don't pass NO_PREFETCH flag implicitly
drm/nouveau: uvmm: fix unset region pointer on remap
drm/nouveau: sched: avoid job races between entities
drm/i915: Fix HPD polling, reenabling the output poll work as needed
drm: Add an HPD poll helper to reschedule the poll work
drm/i915: Fix TLB-Invalidation seqno store
drm/ttm/tests: Fix type conversion in ttm_pool_test
drm/msm/a6xx: Bail out early if setting GPU OOB fails
drm/msm/a6xx: Move LLC accessors to the common header
drm/msm/a6xx: Introduce a6xx_llc_read
drm/ttm/tests: Require MMU when testing
drm/panel: simple: Fix Innolux G156HCE-L01 LVDS clock
Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0""
drm/amdgpu: Add memory vendor information
drm/amd: flush any delayed gfxoff on suspend entry
drm/amdgpu: skip fence GFX interrupts disable/enable for S0ix
drm/amdgpu: Remove gfxoff check in GFX v9.4.3
drm/amd/pm: Update pci link speed for smu v13.0.6
...
This commit is contained in:
Linus Torvalds
@@ -94,6 +94,9 @@ extern "C" {
|
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*
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* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
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* for appending data.
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*
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* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
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* signalling user mode queues.
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*/
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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@@ -101,12 +104,14 @@ extern "C" {
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
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#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
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AMDGPU_GEM_DOMAIN_GTT | \
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AMDGPU_GEM_DOMAIN_VRAM | \
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AMDGPU_GEM_DOMAIN_GDS | \
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AMDGPU_GEM_DOMAIN_GWS | \
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AMDGPU_GEM_DOMAIN_OA)
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AMDGPU_GEM_DOMAIN_OA | \
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AMDGPU_GEM_DOMAIN_DOORBELL)
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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@@ -673,8 +673,11 @@ struct drm_gem_open {
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* Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT
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* and &DRM_PRIME_CAP_EXPORT.
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*
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* PRIME buffers are exposed as dma-buf file descriptors. See
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* Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing".
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* Starting from kernel version 6.6, both &DRM_PRIME_CAP_IMPORT and
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* &DRM_PRIME_CAP_EXPORT are always advertised.
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*
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* PRIME buffers are exposed as dma-buf file descriptors.
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* See :ref:`prime_buffer_sharing`.
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*/
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#define DRM_CAP_PRIME 0x5
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/**
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@@ -682,6 +685,8 @@ struct drm_gem_open {
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*
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* If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME
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* buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.
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*
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* Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
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*/
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#define DRM_PRIME_CAP_IMPORT 0x1
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/**
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@@ -689,6 +694,8 @@ struct drm_gem_open {
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*
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* If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME
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* buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.
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*
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* Starting from kernel version 6.6, this bit is always set in &DRM_CAP_PRIME.
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*/
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#define DRM_PRIME_CAP_EXPORT 0x2
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/**
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@@ -756,15 +763,14 @@ struct drm_gem_open {
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/**
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* DRM_CAP_SYNCOBJ
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*
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* If set to 1, the driver supports sync objects. See
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* Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
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* If set to 1, the driver supports sync objects. See :ref:`drm_sync_objects`.
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*/
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#define DRM_CAP_SYNCOBJ 0x13
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/**
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* DRM_CAP_SYNCOBJ_TIMELINE
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*
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* If set to 1, the driver supports timeline operations on sync objects. See
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* Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
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* :ref:`drm_sync_objects`.
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*/
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#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
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@@ -909,6 +915,27 @@ struct drm_syncobj_timeline_wait {
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__u32 pad;
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};
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/**
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* struct drm_syncobj_eventfd
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* @handle: syncobj handle.
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* @flags: Zero to wait for the point to be signalled, or
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* &DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE to wait for a fence to be
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* available for the point.
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* @point: syncobj timeline point (set to zero for binary syncobjs).
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* @fd: Existing eventfd to sent events to.
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* @pad: Must be zero.
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*
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* Register an eventfd to be signalled by a syncobj. The eventfd counter will
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* be incremented by one.
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*/
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struct drm_syncobj_eventfd {
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__u32 handle;
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__u32 flags;
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__u64 point;
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__s32 fd;
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__u32 pad;
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};
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struct drm_syncobj_array {
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__u64 handles;
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@@ -1169,6 +1196,8 @@ extern "C" {
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*/
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#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
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#define DRM_IOCTL_SYNCOBJ_EVENTFD DRM_IOWR(0xCF, struct drm_syncobj_eventfd)
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/*
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* Device specific ioctls should only be in their respective headers
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* The device specific ioctl range is from 0x40 to 0x9f.
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@@ -1180,25 +1209,50 @@ extern "C" {
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#define DRM_COMMAND_BASE 0x40
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#define DRM_COMMAND_END 0xA0
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/*
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* Header for events written back to userspace on the drm fd. The
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* type defines the type of event, the length specifies the total
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* length of the event (including the header), and user_data is
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* typically a 64 bit value passed with the ioctl that triggered the
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* event. A read on the drm fd will always only return complete
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* events, that is, if for example the read buffer is 100 bytes, and
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* there are two 64 byte events pending, only one will be returned.
|
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/**
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* struct drm_event - Header for DRM events
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* @type: event type.
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* @length: total number of payload bytes (including header).
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*
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* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
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* up are chipset specific.
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* This struct is a header for events written back to user-space on the DRM FD.
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* A read on the DRM FD will always only return complete events: e.g. if the
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* read buffer is 100 bytes large and there are two 64 byte events pending,
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* only one will be returned.
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*
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* Event types 0 - 0x7fffffff are generic DRM events, 0x80000000 and
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* up are chipset specific. Generic DRM events include &DRM_EVENT_VBLANK,
|
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* &DRM_EVENT_FLIP_COMPLETE and &DRM_EVENT_CRTC_SEQUENCE.
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*/
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struct drm_event {
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__u32 type;
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__u32 length;
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};
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/**
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* DRM_EVENT_VBLANK - vertical blanking event
|
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*
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* This event is sent in response to &DRM_IOCTL_WAIT_VBLANK with the
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* &_DRM_VBLANK_EVENT flag set.
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*
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* The event payload is a struct drm_event_vblank.
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*/
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#define DRM_EVENT_VBLANK 0x01
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/**
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* DRM_EVENT_FLIP_COMPLETE - page-flip completion event
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*
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* This event is sent in response to an atomic commit or legacy page-flip with
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* the &DRM_MODE_PAGE_FLIP_EVENT flag set.
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*
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* The event payload is a struct drm_event_vblank.
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*/
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#define DRM_EVENT_FLIP_COMPLETE 0x02
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/**
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* DRM_EVENT_CRTC_SEQUENCE - CRTC sequence event
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*
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* This event is sent in response to &DRM_IOCTL_CRTC_QUEUE_SEQUENCE.
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*
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* The event payload is a struct drm_event_crtc_sequence.
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*/
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#define DRM_EVENT_CRTC_SEQUENCE 0x03
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struct drm_event_vblank {
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@@ -488,6 +488,9 @@ struct drm_mode_get_connector {
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* This is not an object ID. This is a per-type connector number. Each
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* (type, type_id) combination is unique across all connectors of a DRM
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* device.
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*
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* The (type, type_id) combination is not a stable identifier: the
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* type_id can change depending on the driver probe order.
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*/
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__u32 connector_type_id;
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@@ -883,7 +886,7 @@ struct hdr_metadata_infoframe {
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*/
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struct {
|
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__u16 x, y;
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} display_primaries[3];
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} display_primaries[3];
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||||
/**
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||||
* @white_point: White Point of Colorspace Data.
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* These are coded as unsigned 16-bit values in units of
|
||||
@@ -894,7 +897,7 @@ struct hdr_metadata_infoframe {
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*/
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struct {
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__u16 x, y;
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} white_point;
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} white_point;
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/**
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* @max_display_mastering_luminance: Max Mastering Display Luminance.
|
||||
* This value is coded as an unsigned 16-bit value in units of 1 cd/m2,
|
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|
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@@ -60,6 +60,7 @@ extern "C" {
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#define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
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#define DRM_IVPU_PARAM_TILE_CONFIG 11
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#define DRM_IVPU_PARAM_SKU 12
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#define DRM_IVPU_PARAM_CAPABILITIES 13
|
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#define DRM_IVPU_PLATFORM_TYPE_SILICON 0
|
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|
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@@ -68,6 +69,9 @@ extern "C" {
|
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#define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
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#define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
|
||||
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#define DRM_IVPU_CAP_METRIC_STREAMER 1
|
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#define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2
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||||
/**
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* struct drm_ivpu_param - Get/Set VPU parameters
|
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*/
|
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@@ -129,8 +133,10 @@ struct drm_ivpu_param {
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__u64 value;
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};
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#define DRM_IVPU_BO_HIGH_MEM 0x00000001
|
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#define DRM_IVPU_BO_SHAVE_MEM 0x00000001
|
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#define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
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#define DRM_IVPU_BO_MAPPABLE 0x00000002
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#define DRM_IVPU_BO_DMA_MEM 0x00000004
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#define DRM_IVPU_BO_CACHED 0x00000000
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#define DRM_IVPU_BO_UNCACHED 0x00010000
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@@ -140,6 +146,7 @@ struct drm_ivpu_param {
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#define DRM_IVPU_BO_FLAGS \
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(DRM_IVPU_BO_HIGH_MEM | \
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||||
DRM_IVPU_BO_MAPPABLE | \
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||||
DRM_IVPU_BO_DMA_MEM | \
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DRM_IVPU_BO_CACHE_MASK)
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||||
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||||
/**
|
||||
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||||
@@ -33,11 +33,51 @@
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||||
extern "C" {
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#endif
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||||
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#define NOUVEAU_GETPARAM_PCI_VENDOR 3
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#define NOUVEAU_GETPARAM_PCI_DEVICE 4
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||||
#define NOUVEAU_GETPARAM_BUS_TYPE 5
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||||
#define NOUVEAU_GETPARAM_FB_SIZE 8
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#define NOUVEAU_GETPARAM_AGP_SIZE 9
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||||
#define NOUVEAU_GETPARAM_CHIPSET_ID 11
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#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
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#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
|
||||
#define NOUVEAU_GETPARAM_PTIMER_TIME 14
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||||
#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
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#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
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||||
struct drm_nouveau_getparam {
|
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__u64 param;
|
||||
__u64 value;
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};
|
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struct drm_nouveau_channel_alloc {
|
||||
__u32 fb_ctxdma_handle;
|
||||
__u32 tt_ctxdma_handle;
|
||||
|
||||
__s32 channel;
|
||||
__u32 pushbuf_domains;
|
||||
|
||||
/* Notifier memory */
|
||||
__u32 notifier_handle;
|
||||
|
||||
/* DRM-enforced subchannel assignments */
|
||||
struct {
|
||||
__u32 handle;
|
||||
__u32 grclass;
|
||||
} subchan[8];
|
||||
__u32 nr_subchan;
|
||||
};
|
||||
|
||||
struct drm_nouveau_channel_free {
|
||||
__s32 channel;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
|
||||
#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
|
||||
#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
|
||||
#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
|
||||
#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
|
||||
/* The BO will never be shared via import or export. */
|
||||
#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
|
||||
|
||||
#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
|
||||
#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
|
||||
@@ -98,6 +138,7 @@ struct drm_nouveau_gem_pushbuf_push {
|
||||
__u32 pad;
|
||||
__u64 offset;
|
||||
__u64 length;
|
||||
#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pushbuf {
|
||||
@@ -126,16 +167,233 @@ struct drm_nouveau_gem_cpu_fini {
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
#define DRM_NOUVEAU_GETPARAM 0x00 /* deprecated */
|
||||
/**
|
||||
* struct drm_nouveau_sync - sync object
|
||||
*
|
||||
* This structure serves as synchronization mechanism for (potentially)
|
||||
* asynchronous operations such as EXEC or VM_BIND.
|
||||
*/
|
||||
struct drm_nouveau_sync {
|
||||
/**
|
||||
* @flags: the flags for a sync object
|
||||
*
|
||||
* The first 8 bits are used to determine the type of the sync object.
|
||||
*/
|
||||
__u32 flags;
|
||||
#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
|
||||
#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
|
||||
#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
|
||||
/**
|
||||
* @handle: the handle of the sync object
|
||||
*/
|
||||
__u32 handle;
|
||||
/**
|
||||
* @timeline_value:
|
||||
*
|
||||
* The timeline point of the sync object in case the syncobj is of
|
||||
* type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
|
||||
*/
|
||||
__u64 timeline_value;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_nouveau_vm_init - GPU VA space init structure
|
||||
*
|
||||
* Used to initialize the GPU's VA space for a user client, telling the kernel
|
||||
* which portion of the VA space is managed by the UMD and kernel respectively.
|
||||
*
|
||||
* For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
|
||||
* channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
|
||||
* with -ENOSYS.
|
||||
*/
|
||||
struct drm_nouveau_vm_init {
|
||||
/**
|
||||
* @kernel_managed_addr: start address of the kernel managed VA space
|
||||
* region
|
||||
*/
|
||||
__u64 kernel_managed_addr;
|
||||
/**
|
||||
* @kernel_managed_size: size of the kernel managed VA space region in
|
||||
* bytes
|
||||
*/
|
||||
__u64 kernel_managed_size;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_nouveau_vm_bind_op - VM_BIND operation
|
||||
*
|
||||
* This structure represents a single VM_BIND operation. UMDs should pass
|
||||
* an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
|
||||
*/
|
||||
struct drm_nouveau_vm_bind_op {
|
||||
/**
|
||||
* @op: the operation type
|
||||
*/
|
||||
__u32 op;
|
||||
/**
|
||||
* @DRM_NOUVEAU_VM_BIND_OP_MAP:
|
||||
*
|
||||
* Map a GEM object to the GPU's VA space. Optionally, the
|
||||
* &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to
|
||||
* create sparse mappings for the given range.
|
||||
*/
|
||||
#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
|
||||
/**
|
||||
* @DRM_NOUVEAU_VM_BIND_OP_UNMAP:
|
||||
*
|
||||
* Unmap an existing mapping in the GPU's VA space. If the region the mapping
|
||||
* is located in is a sparse region, new sparse mappings are created where the
|
||||
* unmapped (memory backed) mapping was mapped previously. To remove a sparse
|
||||
* region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
|
||||
*/
|
||||
#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
|
||||
/**
|
||||
* @flags: the flags for a &drm_nouveau_vm_bind_op
|
||||
*/
|
||||
__u32 flags;
|
||||
/**
|
||||
* @DRM_NOUVEAU_VM_BIND_SPARSE:
|
||||
*
|
||||
* Indicates that an allocated VA space region should be sparse.
|
||||
*/
|
||||
#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
|
||||
/**
|
||||
* @handle: the handle of the DRM GEM object to map
|
||||
*/
|
||||
__u32 handle;
|
||||
/**
|
||||
* @pad: 32 bit padding, should be 0
|
||||
*/
|
||||
__u32 pad;
|
||||
/**
|
||||
* @addr:
|
||||
*
|
||||
* the address the VA space region or (memory backed) mapping should be mapped to
|
||||
*/
|
||||
__u64 addr;
|
||||
/**
|
||||
* @bo_offset: the offset within the BO backing the mapping
|
||||
*/
|
||||
__u64 bo_offset;
|
||||
/**
|
||||
* @range: the size of the requested mapping in bytes
|
||||
*/
|
||||
__u64 range;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
|
||||
*/
|
||||
struct drm_nouveau_vm_bind {
|
||||
/**
|
||||
* @op_count: the number of &drm_nouveau_vm_bind_op
|
||||
*/
|
||||
__u32 op_count;
|
||||
/**
|
||||
* @flags: the flags for a &drm_nouveau_vm_bind ioctl
|
||||
*/
|
||||
__u32 flags;
|
||||
/**
|
||||
* @DRM_NOUVEAU_VM_BIND_RUN_ASYNC:
|
||||
*
|
||||
* Indicates that the given VM_BIND operation should be executed asynchronously
|
||||
* by the kernel.
|
||||
*
|
||||
* If this flag is not supplied the kernel executes the associated operations
|
||||
* synchronously and doesn't accept any &drm_nouveau_sync objects.
|
||||
*/
|
||||
#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
|
||||
/**
|
||||
* @wait_count: the number of wait &drm_nouveau_syncs
|
||||
*/
|
||||
__u32 wait_count;
|
||||
/**
|
||||
* @sig_count: the number of &drm_nouveau_syncs to signal when finished
|
||||
*/
|
||||
__u32 sig_count;
|
||||
/**
|
||||
* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
|
||||
*/
|
||||
__u64 wait_ptr;
|
||||
/**
|
||||
* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
|
||||
*/
|
||||
__u64 sig_ptr;
|
||||
/**
|
||||
* @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
|
||||
*/
|
||||
__u64 op_ptr;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_nouveau_exec_push - EXEC push operation
|
||||
*
|
||||
* This structure represents a single EXEC push operation. UMDs should pass an
|
||||
* array of this structure via struct drm_nouveau_exec's &push_ptr field.
|
||||
*/
|
||||
struct drm_nouveau_exec_push {
|
||||
/**
|
||||
* @va: the virtual address of the push buffer mapping
|
||||
*/
|
||||
__u64 va;
|
||||
/**
|
||||
* @va_len: the length of the push buffer mapping
|
||||
*/
|
||||
__u32 va_len;
|
||||
/**
|
||||
* @flags: the flags for this push buffer mapping
|
||||
*/
|
||||
__u32 flags;
|
||||
#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
|
||||
};
|
||||
|
||||
/**
|
||||
* struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
|
||||
*/
|
||||
struct drm_nouveau_exec {
|
||||
/**
|
||||
* @channel: the channel to execute the push buffer in
|
||||
*/
|
||||
__u32 channel;
|
||||
/**
|
||||
* @push_count: the number of &drm_nouveau_exec_push ops
|
||||
*/
|
||||
__u32 push_count;
|
||||
/**
|
||||
* @wait_count: the number of wait &drm_nouveau_syncs
|
||||
*/
|
||||
__u32 wait_count;
|
||||
/**
|
||||
* @sig_count: the number of &drm_nouveau_syncs to signal when finished
|
||||
*/
|
||||
__u32 sig_count;
|
||||
/**
|
||||
* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
|
||||
*/
|
||||
__u64 wait_ptr;
|
||||
/**
|
||||
* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
|
||||
*/
|
||||
__u64 sig_ptr;
|
||||
/**
|
||||
* @push_ptr: pointer to &drm_nouveau_exec_push ops
|
||||
*/
|
||||
__u64 push_ptr;
|
||||
};
|
||||
|
||||
#define DRM_NOUVEAU_GETPARAM 0x00
|
||||
#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x03 /* deprecated */
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x03
|
||||
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
|
||||
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
|
||||
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
|
||||
#define DRM_NOUVEAU_NVIF 0x07
|
||||
#define DRM_NOUVEAU_SVM_INIT 0x08
|
||||
#define DRM_NOUVEAU_SVM_BIND 0x09
|
||||
#define DRM_NOUVEAU_VM_INIT 0x10
|
||||
#define DRM_NOUVEAU_VM_BIND 0x11
|
||||
#define DRM_NOUVEAU_EXEC 0x12
|
||||
#define DRM_NOUVEAU_GEM_NEW 0x40
|
||||
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
|
||||
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
|
||||
@@ -188,6 +446,10 @@ struct drm_nouveau_svm_bind {
|
||||
#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
|
||||
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
|
||||
#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
|
||||
#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
|
||||
#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
|
||||
|
||||
@@ -197,6 +459,9 @@ struct drm_nouveau_svm_bind {
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
|
||||
#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
|
||||
|
||||
#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
|
||||
#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
|
||||
#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -64,6 +64,16 @@ struct drm_virtgpu_map {
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01
|
||||
#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \
|
||||
VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
|
||||
0)
|
||||
struct drm_virtgpu_execbuffer_syncobj {
|
||||
__u32 handle;
|
||||
__u32 flags;
|
||||
__u64 point;
|
||||
};
|
||||
|
||||
/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
|
||||
struct drm_virtgpu_execbuffer {
|
||||
__u32 flags;
|
||||
@@ -73,7 +83,11 @@ struct drm_virtgpu_execbuffer {
|
||||
__u32 num_bo_handles;
|
||||
__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
|
||||
__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
|
||||
__u32 pad;
|
||||
__u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */
|
||||
__u32 num_in_syncobjs;
|
||||
__u32 num_out_syncobjs;
|
||||
__u64 in_syncobjs;
|
||||
__u64 out_syncobjs;
|
||||
};
|
||||
|
||||
#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
|
||||
|
||||
Reference in New Issue
Block a user