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rk3066b: add CPU_CLK_DIV

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chenxing
2012-08-30 14:56:42 +08:00
parent b64db69ac9
commit 467f500c6b
1 changed files with 11 additions and 3 deletions
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14
arch/arm/mach-rk30/include/mach/cru-rk3066b.h
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@@ -109,13 +109,21 @@ enum rk_plls_id {
#define CORE_SEL_APLL (0 << 8)
#define CORE_SEL_GPLL (1 << 8)
#define CORE_CLK_DIV_W_MSK (0x1F << 16)
#define CORE_CLK_DIV_MSK (0x1F)
#define CORE_CLK_DIV_W_MSK (0x1F << 25)
#define CORE_CLK_DIV_MSK (0x1F << 9)
#define CORE_CLK_DIV(i) (((i) - 1) & 0x1F)
#define CPU_SEL_PLL_MSK (1 << 5)
#define CPU_SEL_PLL_W_MSK (1 << 21)
#define CPU_SEL_APLL (0 << 5)
#define CPU_SEL_GPLL (1 << 5)
#define CPU_CLK_DIV_W_MSK (0x1F << 16)
#define CPU_CLK_DIV_MSK (0x1F)
#define CPU_CLK_DIV(i) (((i) - 1) & 0x1F)
/*******************CLKSEL1 BITS***************************/
//aclk div
#define GET_CORE_ACLK_VAL(reg) ((reg)>=4 ?8:((reg)+1))
#define CPU_ACLK_W_MSK (7 << 16)