From 47a1e8c99296bc0cdbe374b6c52c50db9002a16c Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 19 Nov 2021 19:15:14 +0800 Subject: [PATCH] drm/rockchip: vop2: Only do clk_round_rate check when dclk <= max_dclk The Current max vop_dclk if 600MHZ on all rockchip soc. Signed-off-by: Andy Yan Change-Id: I497fc14e89bcbaf4e6aa44fc36bc7fc93ac45aed --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index e16253d30e03..9906d38e7b10 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -139,6 +139,8 @@ #define VOP2_SYS_AXI_BUS_NUM 2 #define VOP2_MAX_VP_OUTPUT_WIDTH 4096 +/* KHZ */ +#define VOP2_MAX_DCLK_RATE 600000 #define VOP2_COLOR_KEY_NONE (0 << 31) #define VOP2_COLOR_KEY_MASK (1 << 31) @@ -4869,9 +4871,9 @@ static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc, if (mode->flags & DRM_MODE_FLAG_DBLCLK) adj_mode->crtc_clock *= 2; - adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk, - adj_mode->crtc_clock * 1000), 1000); - + if (adj_mode->crtc_clock <= VOP2_MAX_DCLK_RATE) + adj_mode->crtc_clock = DIV_ROUND_UP(clk_round_rate(vp->dclk, + adj_mode->crtc_clock * 1000), 1000); return true; }