From 47a2e88510ce92c20177566e5abb3293d369ba38 Mon Sep 17 00:00:00 2001
From: Huang zhibao <hzb@rock-chips.com>
Date: Wed, 29 Apr 2020 04:43:09 -0400
Subject: [PATCH] ARM: dts: rockchip: add ai-cam-ddr3-v1 dts for ai cam ddr3
 board

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Ic9a504a3a8fe9465101a353640254259c952ae6b
---
 arch/arm/boot/dts/Makefile                  |  1 +
 arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts | 65 +++++++++++++++++++++
 2 files changed, 66 insertions(+)
 create mode 100644 arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cf991f8a8836..51db28a1a2f9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -845,6 +845,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
 	rv1109-evb-ddr3-v10.dtb \
 	rv1109-evb-lp3-v10.dtb \
 	rv1109-fpga.dtb \
+	rv1126-ai-cam-ddr3-v1.dtb \
 	rv1126-evb-ddr3-v10.dtb \
 	rv1126-evb-ddr3-v10-tb.dtb \
 	rv1126-evb-lp3-v10.dtb \
diff --git a/arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts b/arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts
new file mode 100644
index 000000000000..c3944cfc954d
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-ai-cam-ddr3-v1.dts
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv11xx-ai-cam.dtsi"
+
+/ {
+	model = "Rockchip RV1126 AI CAMERA DDR3L Board";
+	compatible = "rockchip,rv1126-ai-cam-ddr3L-v1", "rockchip,rv1126";
+
+	chosen {
+		bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait snd_aloop.index=7";
+	};
+};
+
+&csi_dphy0 {
+	status = "okay";
+
+	ports {
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi_in_ucam0: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&ucam_out0>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <400000>;
+
+	gc4c33: gc4c33@29 {
+		compatible = "galaxycore,gc4c33";
+		reg = <0x29>;
+		clocks = <&cru CLK_MIPICSI_OUT>;
+		clock-names = "xvclk";
+		power-domains = <&power RV1126_PD_VI>;
+		pinctrl-names = "rockchip,camera_default";
+		pinctrl-0 = <&mipi_csi_clk0>;
+		pwren-gpios= <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
+		pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <1>;
+		rockchip,camera-module-facing = "front";
+		rockchip,camera-module-name = "JSD3425-C1";
+		rockchip,camera-module-lens-name = "JSD3425-C1";
+		// NO_HDR:0 HDR_X2:5 HDR_X3:6
+		rockchip,camera-hdr-mode = <0>;
+		port {
+			ucam_out0: endpoint {
+				remote-endpoint = <&mipi_in_ucam0>;
+				data-lanes = <1 2>;
+			};
+		};
+	};
+};
\ No newline at end of file