From 47e86f6791335a2dccac25f47f458264eaea7b5d Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Thu, 5 Aug 2021 10:52:55 +0800 Subject: [PATCH] arm64: mm: export __flush_dcache_all Change-Id: I268a515f98361a4fd152d399262307aadb058344 Signed-off-by: Jianqun Xu --- arch/arm64/include/asm/cacheflush.h | 1 + arch/arm64/mm/cache.S | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h index 3f8a615bfc82..a4fa4b50712a 100644 --- a/arch/arm64/include/asm/cacheflush.h +++ b/arch/arm64/include/asm/cacheflush.h @@ -79,6 +79,7 @@ extern void flush_cache_all(void); extern void __flush_icache_range(unsigned long start, unsigned long end); extern int invalidate_icache_range(unsigned long start, unsigned long end); +extern void __flush_dcache_all(void); extern void __flush_dcache_area(void *addr, size_t len); extern void __inval_dcache_area(void *addr, size_t len); extern void __clean_dcache_area_poc(void *addr, size_t len); diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S index 000fb4465414..7fdea6b62ab0 100644 --- a/arch/arm64/mm/cache.S +++ b/arch/arm64/mm/cache.S @@ -32,7 +32,7 @@ * * Corrupted registers: x0-x7, x9-x11 */ -__flush_dcache_all: +ENTRY(__flush_dcache_all) dmb sy // ensure ordering with previous memory accesses mrs x0, clidr_el1 // read clidr and x3, x0, #0x7000000 // extract loc from clidr