From 48fe27347d9c43e7a1d3af2ca3c9be8c18cd35c2 Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Fri, 19 Jan 2018 09:47:01 +0800 Subject: [PATCH] clk: meson: axg: fix the od shift of the sys_pll PD#159137: clk: meson: axg: fix the od shift of the sys_pll According to datasheet, the od shift of sys_pll is 16, fix the typo which introduced at previous commit. Change-Id: I8d7e36b1178c0ab7f89791964fe4bb216c551d6d Signed-off-by: Yixun Lan --- drivers/amlogic/clk/axg/axg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/amlogic/clk/axg/axg.c b/drivers/amlogic/clk/axg/axg.c index 5aa86e246e3f..25b1d94aa8e8 100644 --- a/drivers/amlogic/clk/axg/axg.c +++ b/drivers/amlogic/clk/axg/axg.c @@ -88,7 +88,7 @@ static struct meson_clk_pll axg_sys_pll = { }, .od = { .reg_off = HHI_SYS_PLL_CNTL, - .shift = 10, + .shift = 16, .width = 2, }, .rate_table = sys_pll_rate_table,