From 494285b57faff3bb387eadd0a9da896a1db39c05 Mon Sep 17 00:00:00 2001
From: Finley Xiao <finley.xiao@rock-chips.com>
Date: Thu, 24 Oct 2019 20:19:15 +0800
Subject: [PATCH] clk: rockchip: px30: Add pll name for cpuclk

Change-Id: I4302071cfd29148fb33ba096f5f3bc2aeff1406e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
---
 drivers/clk/rockchip/clk-px30.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-px30.c b/drivers/clk/rockchip/clk-px30.c
index f3c23e6b873d..b20361faca97 100644
--- a/drivers/clk/rockchip/clk-px30.c
+++ b/drivers/clk/rockchip/clk-px30.c
@@ -140,6 +140,7 @@ static const struct rockchip_cpuclk_reg_data px30_cpuclk_data = {
 	.mux_core_main = 0,
 	.mux_core_shift = 7,
 	.mux_core_mask = 0x1,
+	.pll_name = "pll_apll",
 };
 
 PNAME(mux_pll_p)		= { "xin24m"};