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Merge commit '73b5dde370957bcfddb30e2ac5a3cd4f56197824'

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* commit '73b5dde370957bcfddb30e2ac5a3cd4f56197824': (223 commits)
  MALI: bifrost: Not to call kbase_ipa_reset_data() if rockchip simple-power-model is used
  arm64: dts: rockchip: add camera dtsi on rk3562-evb2-ddr4-v10-linux.dts
  arm64: dts: rockchip: Assign VOP_ACLK to 750MHZ for rk3588-linux.dtsi
  pwm: rockchip: enable dclk scale function in oneshot mode
  soc: rockchip_system_monitor: Fix TPYE -> TYPE typo
  media: i2c: max96712: version 1.05.00
  drm/panel: maxim-max96752f: Fix pin assignment
  soc: rockchip: tb_service: unmask mcu_done after all registered cb were finished
  arm64: dts: rockchip: rk3588s: Fix low-volt-mem-read-margin
  arm64: dts: rockchip: rk3588: Fixed the rkvenc1 init frequency
  phy: rockchip: samsung-dcphy: restart rx after apb reset when rx is streaming
  fiq_debugger: tty write to tty fifo
  ARM: dts: rockchip: rv1106 boards: Add sdmmc idle state support
  ARM: dts: rockchip: rv1126: Add sdmmc idle state support
  ARM: dts: rockchip: add idle state for sdmmc of rv1106-pinctrl
  ARM: dts: rockchip: add idle state for sdmmc of rv1126-pinctrl
  media: i2c: max96712: version 1.04.00
  media: rockchip: vicap: fixes s_selection, support to set crop area
  media: rockchip: vicap: only enum outout formats that terminal sensor support to use
  media: rockchip: vicap: add security testing for output format
  ...

Change-Id: Ie80fc4f1a5e335dccf6aa564515adfd78f69d62f
This commit is contained in:
Tao Huang
2023-06-14 15:24:28 +08:00
parent 006bf05745 73b5dde370
commit 495689db2e
295 changed files with 18345 additions and 7416 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
include/uapi/drm/rockchip_drm.h
View File

@@ -15,8 +15,13 @@
#ifndef _UAPI_ROCKCHIP_DRM_H
#define _UAPI_ROCKCHIP_DRM_H
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#include <drm/drm.h>
#include <drm/drm_file.h>
/*
* Send vcnt event instead of blocking,
@@ -105,10 +110,6 @@ enum rockchip_cabc_mode {
ROCKCHIP_DRM_CABC_MODE_USERSPACE,
};
struct drm_rockchip_vcnt_event {
struct drm_pending_event base;
};
#define DRM_ROCKCHIP_GEM_CREATE 0x00
#define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01
#define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02

12
include/uapi/gpu/arm/bifrost/backend/gpu/mali_kbase_model_linux.h
View File

@@ -27,12 +27,10 @@
#define _UAPI_KBASE_MODEL_LINUX_H_
/* Generic model IRQs */
enum model_linux_irqs {
MODEL_LINUX_JOB_IRQ,
MODEL_LINUX_GPU_IRQ,
MODEL_LINUX_MMU_IRQ,
MODEL_LINUX_NONE_IRQ,
MODEL_LINUX_NUM_TYPE_IRQ
};
#define MODEL_LINUX_JOB_IRQ (0x1 << 0)
#define MODEL_LINUX_GPU_IRQ (0x1 << 1)
#define MODEL_LINUX_MMU_IRQ (0x1 << 2)
#define MODEL_LINUX_IRQ_MASK (MODEL_LINUX_JOB_IRQ | MODEL_LINUX_GPU_IRQ | MODEL_LINUX_MMU_IRQ)
#endif /* _UAPI_KBASE_MODEL_LINUX_H_ */

3
include/uapi/gpu/arm/bifrost/csf/mali_base_csf_kernel.h
View File

@@ -145,6 +145,9 @@
#define BASE_CSF_TILER_OOM_EXCEPTION_FLAG (1u << 0)
#define BASE_CSF_EXCEPTION_HANDLER_FLAGS_MASK (BASE_CSF_TILER_OOM_EXCEPTION_FLAG)
/* Initial value for LATEST_FLUSH register */
#define POWER_DOWN_LATEST_FLUSH_VALUE ((uint32_t)1)
/**
* enum base_kcpu_command_type - Kernel CPU queue command type.
* @BASE_KCPU_COMMAND_TYPE_FENCE_SIGNAL: fence_signal,

6
include/uapi/gpu/arm/bifrost/csf/mali_kbase_csf_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -79,11 +79,13 @@
* - prfcnt_block_metadata::block_idx gaps.
* - PRFCNT_CONTROL_CMD_SAMPLE_ASYNC is removed.
* 1.18:
* - Relax the requirement to create a mapping with BASE_MEM_MAP_TRACKING_HANDLE
* before allocating GPU memory for the context.
* - CPU mappings of USER_BUFFER imported memory handles must be cached.
*/
#define BASE_UK_VERSION_MAJOR 1
#define BASE_UK_VERSION_MINOR 17
#define BASE_UK_VERSION_MINOR 18
/**
* struct kbase_ioctl_version_check - Check version compatibility between

11
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_csf.h
View File

@@ -27,4 +27,15 @@
#define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE + (r))
#define STATUS 0x004 /* (RO) Status register */
/* USER base address */
#define USER_BASE 0x0010000
#define USER_REG(r) (USER_BASE + (r))
/* USER register offsets */
#define LATEST_FLUSH 0x0000 /* () Flush ID of latest clean-and-invalidate operation */
/* DOORBELLS base address */
#define DOORBELLS_BASE 0x0080000
#define DOORBELLS_REG(r) (DOORBELLS_BASE + (r))
#endif /* _UAPI_KBASE_GPU_REGMAP_CSF_H_ */

4
include/uapi/gpu/arm/bifrost/gpu/backend/mali_kbase_gpu_regmap_jm.h
View File

@@ -43,4 +43,8 @@
#define JS_CONFIG_NEXT 0x58 /* (RW) Next configuration settings for job slot n */
#define JS_COMMAND_NEXT 0x60 /* (RW) Next command register for job slot n */
#define JOB_SLOT0 0x800 /* Configuration registers for job slot 0 */
#define JOB_SLOT_REG(n, r) (JOB_CONTROL_REG(JOB_SLOT0 + ((n) << 7)) + (r))
#endif /* _UAPI_KBASE_GPU_REGMAP_JM_H_ */

7
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_regmap.h
View File

@@ -36,6 +36,9 @@
#define GPU_ID 0x000 /* (RO) GPU and revision identifier */
#define GPU_IRQ_CLEAR 0x024 /* (WO) */
#define GPU_IRQ_STATUS 0x02C /* (RO) */
#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
@@ -62,6 +65,7 @@
#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
#define JOB_IRQ_STATUS 0x00C /* Interrupt status register */
/* MMU control registers */
@@ -70,6 +74,9 @@
#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
#define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */
#define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */
#define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */
#define MMU_AS0 0x400 /* Configuration registers for address space 0 */

6
include/uapi/gpu/arm/bifrost/jm/mali_kbase_jm_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2022 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -140,10 +140,12 @@
* - prfcnt_block_metadata::block_idx gaps.
* - PRFCNT_CONTROL_CMD_SAMPLE_ASYNC is removed.
* 11.38:
* - Relax the requirement to create a mapping with BASE_MEM_MAP_TRACKING_HANDLE
* before allocating GPU memory for the context.
* - CPU mappings of USER_BUFFER imported memory handles must be cached.
*/
#define BASE_UK_VERSION_MAJOR 11
#define BASE_UK_VERSION_MINOR 37
#define BASE_UK_VERSION_MINOR 38
/**
* struct kbase_ioctl_version_check - Check version compatibility between

24
include/uapi/linux/fec-config.h
View File

@@ -11,22 +11,22 @@
#define FEC_API_VERSION KERNEL_VERSION(1, 0, 0)
struct fec_config {
u32 mesh_density;
u32 src_width;
u32 src_height;
u32 dst_width;
u32 dst_height;
u32 mesh_size;
s32 buf_fd;
u32 fec_bic_mode;
__u32 mesh_density;
__u32 src_width;
__u32 src_height;
__u32 dst_width;
__u32 dst_height;
__u32 mesh_size;
__s32 buf_fd;
__u32 fec_bic_mode;
} __attribute__ ((packed));
struct fec_params_cfg {
u32 module_en_update;
u32 module_ens;
u32 module_cfg_update;
__u32 module_en_update;
__u32 module_ens;
__u32 module_cfg_update;
u32 frame_id;
__u32 frame_id;
struct fec_config fec_cfg;
} __attribute__ ((packed));

28
include/uapi/linux/rk-camera-module.h
View File

@@ -177,13 +177,13 @@
_IOW('V', BASE_VIDIOC_PRIVATE + 38, __u32)
struct rkmodule_i2cdev_info {
u8 slave_addr;
__u8 slave_addr;
} __attribute__ ((packed));
struct rkmodule_dev_info {
union {
struct rkmodule_i2cdev_info i2c_dev;
u32 reserved[8];
__u32 reserved[8];
};
} __attribute__ ((packed));
@@ -693,10 +693,10 @@ enum rkmodule_sync_mode {
};
struct rkmodule_mclk_data {
u32 enable;
u32 mclk_index;
u32 mclk_rate;
u32 reserved[8];
__u32 enable;
__u32 mclk_index;
__u32 mclk_rate;
__u32 reserved[8];
};
/*
@@ -746,14 +746,14 @@ enum csi2_dphy_vendor {
};
struct rkmodule_csi_dphy_param {
u32 vendor;
u32 lp_vol_ref;
u32 lp_hys_sw[DPHY_MAX_LANE];
u32 lp_escclk_pol_sel[DPHY_MAX_LANE];
u32 skew_data_cal_clk[DPHY_MAX_LANE];
u32 clk_hs_term_sel;
u32 data_hs_term_sel[DPHY_MAX_LANE];
u32 reserved[32];
__u32 vendor;
__u32 lp_vol_ref;
__u32 lp_hys_sw[DPHY_MAX_LANE];
__u32 lp_escclk_pol_sel[DPHY_MAX_LANE];
__u32 skew_data_cal_clk[DPHY_MAX_LANE];
__u32 clk_hs_term_sel;
__u32 data_hs_term_sel[DPHY_MAX_LANE];
__u32 reserved[32];
};
struct rkmodule_sensor_fmt {

10
include/uapi/linux/rk-isp1-config.h
View File

@@ -369,7 +369,7 @@ struct cifisp_awb_meas_config {
unsigned char frames;
unsigned char awb_ref_cr;
unsigned char awb_ref_cb;
bool enable_ymax_cmp;
_Bool enable_ymax_cmp;
} __attribute__ ((packed));
/**
@@ -548,14 +548,14 @@ struct cifisp_dpf_nll {
struct cifisp_dpf_rb_flt {
enum cifisp_dpf_rb_filtersize fltsize;
unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS];
bool r_enable;
bool b_enable;
_Bool r_enable;
_Bool b_enable;
} __attribute__ ((packed));
struct cifisp_dpf_g_flt {
unsigned char spatial_coeff[CIFISP_DPF_MAX_SPATIAL_COEFFS];
bool gr_enable;
bool gb_enable;
_Bool gr_enable;
_Bool gb_enable;
} __attribute__ ((packed));
struct cifisp_dpf_gain {

2189
include/uapi/linux/rk-isp2-config.h
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File diff suppressed because it is too large Load Diff

1211
include/uapi/linux/rk-isp21-config.h
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File diff suppressed because it is too large Load Diff

1418
include/uapi/linux/rk-isp3-config.h
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File diff suppressed because it is too large Load Diff

1736
include/uapi/linux/rk-isp32-config.h
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File diff suppressed because it is too large Load Diff

356
include/uapi/linux/rk-ispp-config.h
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@@ -18,14 +18,14 @@
#define ISPP_ID_ORB (4)
#define ISPP_ID_MAX (5)
#define ISPP_MODULE_TNR BIT(ISPP_ID_TNR)//2TO1
#define ISPP_MODULE_TNR BIT(ISPP_ID_TNR)/* 2TO1 */
#define ISPP_MODULE_NR BIT(ISPP_ID_NR)
#define ISPP_MODULE_SHP BIT(ISPP_ID_SHP)
#define ISPP_MODULE_FEC BIT(ISPP_ID_FEC)//CALIBRATION
#define ISPP_MODULE_FEC BIT(ISPP_ID_FEC)/* CALIBRATION */
#define ISPP_MODULE_ORB BIT(ISPP_ID_ORB)
//extra function
/* extra function */
#define ISPP_MODULE_TNR_3TO1 (BIT(16) | ISPP_MODULE_TNR)
#define ISPP_MODULE_FEC_ST (BIT(17) | ISPP_MODULE_FEC)//STABILIZATION
#define ISPP_MODULE_FEC_ST (BIT(17) | ISPP_MODULE_FEC)/* STABILIZATION */
#define TNR_SIGMA_CURVE_SIZE 17
#define TNR_LUMA_CURVE_SIZE 6
@@ -129,157 +129,157 @@ struct rkispp_fec_in_out {
};
struct rkispp_buf_idxfd {
u32 buf_num;
u32 index[MAX_BUF_IDXFD_NUM];
s32 dmafd[MAX_BUF_IDXFD_NUM];
__u32 buf_num;
__u32 index[MAX_BUF_IDXFD_NUM];
__s32 dmafd[MAX_BUF_IDXFD_NUM];
} __attribute__ ((packed));
struct rkispp_trigger_mode {
u32 module;
u32 on;
__u32 module;
__u32 on;
} __attribute__ ((packed));
struct rkispp_tnr_config {
u8 opty_en;
u8 optc_en;
u8 gain_en;
u8 pk0_y;
u8 pk1_y;
u8 pk0_c;
u8 pk1_c;
u8 glb_gain_cur_sqrt;
u8 sigma_x[TNR_SIGMA_CURVE_SIZE - 1];
u8 gfcoef_y0[TNR_GFCOEF6_SIZE];
u8 gfcoef_y1[TNR_GFCOEF3_SIZE];
u8 gfcoef_y2[TNR_GFCOEF3_SIZE];
u8 gfcoef_y3[TNR_GFCOEF3_SIZE];
u8 gfcoef_yg0[TNR_GFCOEF6_SIZE];
u8 gfcoef_yg1[TNR_GFCOEF3_SIZE];
u8 gfcoef_yg2[TNR_GFCOEF3_SIZE];
u8 gfcoef_yg3[TNR_GFCOEF3_SIZE];
u8 gfcoef_yl0[TNR_GFCOEF6_SIZE];
u8 gfcoef_yl1[TNR_GFCOEF3_SIZE];
u8 gfcoef_yl2[TNR_GFCOEF3_SIZE];
u8 gfcoef_cg0[TNR_GFCOEF6_SIZE];
u8 gfcoef_cg1[TNR_GFCOEF3_SIZE];
u8 gfcoef_cg2[TNR_GFCOEF3_SIZE];
u8 gfcoef_cl0[TNR_GFCOEF6_SIZE];
u8 gfcoef_cl1[TNR_GFCOEF3_SIZE];
u8 weight_y[TNR_WEIGHT_Y_SIZE];
__u8 opty_en;
__u8 optc_en;
__u8 gain_en;
__u8 pk0_y;
__u8 pk1_y;
__u8 pk0_c;
__u8 pk1_c;
__u8 glb_gain_cur_sqrt;
__u8 sigma_x[TNR_SIGMA_CURVE_SIZE - 1];
__u8 gfcoef_y0[TNR_GFCOEF6_SIZE];
__u8 gfcoef_y1[TNR_GFCOEF3_SIZE];
__u8 gfcoef_y2[TNR_GFCOEF3_SIZE];
__u8 gfcoef_y3[TNR_GFCOEF3_SIZE];
__u8 gfcoef_yg0[TNR_GFCOEF6_SIZE];
__u8 gfcoef_yg1[TNR_GFCOEF3_SIZE];
__u8 gfcoef_yg2[TNR_GFCOEF3_SIZE];
__u8 gfcoef_yg3[TNR_GFCOEF3_SIZE];
__u8 gfcoef_yl0[TNR_GFCOEF6_SIZE];
__u8 gfcoef_yl1[TNR_GFCOEF3_SIZE];
__u8 gfcoef_yl2[TNR_GFCOEF3_SIZE];
__u8 gfcoef_cg0[TNR_GFCOEF6_SIZE];
__u8 gfcoef_cg1[TNR_GFCOEF3_SIZE];
__u8 gfcoef_cg2[TNR_GFCOEF3_SIZE];
__u8 gfcoef_cl0[TNR_GFCOEF6_SIZE];
__u8 gfcoef_cl1[TNR_GFCOEF3_SIZE];
__u8 weight_y[TNR_WEIGHT_Y_SIZE];
u16 glb_gain_cur __attribute__((aligned(2)));
u16 glb_gain_nxt;
u16 glb_gain_cur_div;
u16 txt_th1_y;
u16 txt_th0_c;
u16 txt_th1_c;
u16 txt_thy_dlt;
u16 txt_thc_dlt;
u16 txt_th0_y;
u16 sigma_y[TNR_SIGMA_CURVE_SIZE];
u16 luma_curve[TNR_LUMA_CURVE_SIZE];
u16 scale_yg[TNR_SCALE_YG_SIZE];
u16 scale_yl[TNR_SCALE_YL_SIZE];
u16 scale_cg[TNR_SCALE_CG_SIZE];
u16 scale_y2cg[TNR_SCALE_Y2CG_SIZE];
u16 scale_cl[TNR_SCALE_CL_SIZE];
u16 scale_y2cl[TNR_SCALE_Y2CL_SIZE];
__u16 glb_gain_cur __attribute__((aligned(2)));
__u16 glb_gain_nxt;
__u16 glb_gain_cur_div;
__u16 txt_th1_y;
__u16 txt_th0_c;
__u16 txt_th1_c;
__u16 txt_thy_dlt;
__u16 txt_thc_dlt;
__u16 txt_th0_y;
__u16 sigma_y[TNR_SIGMA_CURVE_SIZE];
__u16 luma_curve[TNR_LUMA_CURVE_SIZE];
__u16 scale_yg[TNR_SCALE_YG_SIZE];
__u16 scale_yl[TNR_SCALE_YL_SIZE];
__u16 scale_cg[TNR_SCALE_CG_SIZE];
__u16 scale_y2cg[TNR_SCALE_Y2CG_SIZE];
__u16 scale_cl[TNR_SCALE_CL_SIZE];
__u16 scale_y2cl[TNR_SCALE_Y2CL_SIZE];
} __attribute__ ((packed));
struct rkispp_nr_config {
u8 uvnr_step1_en;
u8 uvnr_step2_en;
u8 nr_gain_en;
u8 uvnr_sd32_self_en;
u8 uvnr_nobig_en;
u8 uvnr_big_en;
u8 uvnr_gain_1sigma;
u8 uvnr_gain_offset;
u8 uvnr_gain_t2gen;
u8 uvnr_gain_iso;
u8 uvnr_t1gen_m3alpha;
u8 uvnr_t1flt_mode;
u8 uvnr_t1flt_wtp;
u8 uvnr_t2gen_m3alpha;
u8 uvnr_t2gen_wtp;
u8 uvnr_gain_uvgain[NR_UVNR_UVGAIN_SIZE];
u8 uvnr_t1flt_wtq[NR_UVNR_T1FLT_WTQ_SIZE];
u8 uvnr_t2gen_wtq[NR_UVNR_T2GEN_WTQ_SIZE];
u8 uvnr_t2flt_wtp;
u8 uvnr_t2flt_wt[NR_UVNR_T2FLT_WT_SIZE];
u8 ynr_sgm_dx[NR_YNR_SGM_DX_SIZE];
u8 ynr_lci[NR_YNR_CI_SIZE];
u8 ynr_lgain_min[NR_YNR_LGAIN_MIN_SIZE];
u8 ynr_lgain_max;
u8 ynr_lmerge_bound;
u8 ynr_lmerge_ratio;
u8 ynr_lweit_flt[NR_YNR_LWEIT_FLT_SIZE];
u8 ynr_hlci[NR_YNR_CI_SIZE];
u8 ynr_lhci[NR_YNR_CI_SIZE];
u8 ynr_hhci[NR_YNR_CI_SIZE];
u8 ynr_hgain_sgm[NR_YNR_HGAIN_SGM_SIZE];
u8 ynr_hweit_d[NR_YNR_HWEIT_D_SIZE];
u8 ynr_hgrad_y[NR_YNR_HGRAD_Y_SIZE];
u8 ynr_hmax_adjust;
u8 ynr_hstrength;
u8 ynr_lweit_cmp[NR_YNR_LWEIT_CMP_SIZE];
u8 ynr_lmaxgain_lv4;
__u8 uvnr_step1_en;
__u8 uvnr_step2_en;
__u8 nr_gain_en;
__u8 uvnr_sd32_self_en;
__u8 uvnr_nobig_en;
__u8 uvnr_big_en;
__u8 uvnr_gain_1sigma;
__u8 uvnr_gain_offset;
__u8 uvnr_gain_t2gen;
__u8 uvnr_gain_iso;
__u8 uvnr_t1gen_m3alpha;
__u8 uvnr_t1flt_mode;
__u8 uvnr_t1flt_wtp;
__u8 uvnr_t2gen_m3alpha;
__u8 uvnr_t2gen_wtp;
__u8 uvnr_gain_uvgain[NR_UVNR_UVGAIN_SIZE];
__u8 uvnr_t1flt_wtq[NR_UVNR_T1FLT_WTQ_SIZE];
__u8 uvnr_t2gen_wtq[NR_UVNR_T2GEN_WTQ_SIZE];
__u8 uvnr_t2flt_wtp;
__u8 uvnr_t2flt_wt[NR_UVNR_T2FLT_WT_SIZE];
__u8 ynr_sgm_dx[NR_YNR_SGM_DX_SIZE];
__u8 ynr_lci[NR_YNR_CI_SIZE];
__u8 ynr_lgain_min[NR_YNR_LGAIN_MIN_SIZE];
__u8 ynr_lgain_max;
__u8 ynr_lmerge_bound;
__u8 ynr_lmerge_ratio;
__u8 ynr_lweit_flt[NR_YNR_LWEIT_FLT_SIZE];
__u8 ynr_hlci[NR_YNR_CI_SIZE];
__u8 ynr_lhci[NR_YNR_CI_SIZE];
__u8 ynr_hhci[NR_YNR_CI_SIZE];
__u8 ynr_hgain_sgm[NR_YNR_HGAIN_SGM_SIZE];
__u8 ynr_hweit_d[NR_YNR_HWEIT_D_SIZE];
__u8 ynr_hgrad_y[NR_YNR_HGRAD_Y_SIZE];
__u8 ynr_hmax_adjust;
__u8 ynr_hstrength;
__u8 ynr_lweit_cmp[NR_YNR_LWEIT_CMP_SIZE];
__u8 ynr_lmaxgain_lv4;
u16 uvnr_t1flt_msigma __attribute__((aligned(2)));
u16 uvnr_t2gen_msigma;
u16 uvnr_t2flt_msigma;
u16 ynr_lsgm_y[NR_YNR_SGM_Y_SIZE];
u16 ynr_hsgm_y[NR_YNR_SGM_Y_SIZE];
u16 ynr_hweit[NR_YNR_HWEIT_SIZE];
u16 ynr_hstv_y[NR_YNR_HSTV_Y_SIZE];
u16 ynr_st_scale[NR_YNR_ST_SCALE_SIZE];
__u16 uvnr_t1flt_msigma __attribute__((aligned(2)));
__u16 uvnr_t2gen_msigma;
__u16 uvnr_t2flt_msigma;
__u16 ynr_lsgm_y[NR_YNR_SGM_Y_SIZE];
__u16 ynr_hsgm_y[NR_YNR_SGM_Y_SIZE];
__u16 ynr_hweit[NR_YNR_HWEIT_SIZE];
__u16 ynr_hstv_y[NR_YNR_HSTV_Y_SIZE];
__u16 ynr_st_scale[NR_YNR_ST_SCALE_SIZE];
} __attribute__ ((packed));
struct rkispp_sharp_config {
u8 rotation;
u8 scl_down_v;
u8 scl_down_h;
u8 tile_ycnt;
u8 tile_xcnt;
u8 alpha_adp_en;
u8 yin_flt_en;
u8 edge_avg_en;
u8 ehf_th;
u8 pbf_ratio;
u8 edge_thed;
u8 dir_min;
u8 pbf_shf_bits;
u8 mbf_shf_bits;
u8 hbf_shf_bits;
u8 m_ratio;
u8 h_ratio;
u8 pbf_k[SHP_PBF_KERNEL_SIZE];
u8 mrf_k[SHP_MRF_KERNEL_SIZE];
u8 mbf_k[SHP_MBF_KERNEL_SIZE];
u8 hrf_k[SHP_HRF_KERNEL_SIZE];
u8 hbf_k[SHP_HBF_KERNEL_SIZE];
s8 eg_coef[SHP_EDGE_COEF_SIZE];
u8 eg_smoth[SHP_EDGE_SMOTH_SIZE];
u8 eg_gaus[SHP_EDGE_GAUS_SIZE];
s8 dog_k[SHP_DOG_KERNEL_SIZE];
u8 lum_point[SHP_LUM_POINT_SIZE];
u8 pbf_sigma[SHP_SIGMA_SIZE];
u8 lum_clp_m[SHP_LUM_CLP_SIZE];
s8 lum_min_m[SHP_LUM_MIN_SIZE];
u8 mbf_sigma[SHP_SIGMA_SIZE];
u8 lum_clp_h[SHP_LUM_CLP_SIZE];
u8 hbf_sigma[SHP_SIGMA_SIZE];
u8 edge_lum_thed[SHP_EDGE_LUM_THED_SIZE];
u8 clamp_pos[SHP_CLAMP_SIZE];
u8 clamp_neg[SHP_CLAMP_SIZE];
u8 detail_alpha[SHP_DETAIL_ALPHA_SIZE];
__u8 rotation;
__u8 scl_down_v;
__u8 scl_down_h;
__u8 tile_ycnt;
__u8 tile_xcnt;
__u8 alpha_adp_en;
__u8 yin_flt_en;
__u8 edge_avg_en;
__u8 ehf_th;
__u8 pbf_ratio;
__u8 edge_thed;
__u8 dir_min;
__u8 pbf_shf_bits;
__u8 mbf_shf_bits;
__u8 hbf_shf_bits;
__u8 m_ratio;
__u8 h_ratio;
__u8 pbf_k[SHP_PBF_KERNEL_SIZE];
__u8 mrf_k[SHP_MRF_KERNEL_SIZE];
__u8 mbf_k[SHP_MBF_KERNEL_SIZE];
__u8 hrf_k[SHP_HRF_KERNEL_SIZE];
__u8 hbf_k[SHP_HBF_KERNEL_SIZE];
__s8 eg_coef[SHP_EDGE_COEF_SIZE];
__u8 eg_smoth[SHP_EDGE_SMOTH_SIZE];
__u8 eg_gaus[SHP_EDGE_GAUS_SIZE];
__s8 dog_k[SHP_DOG_KERNEL_SIZE];
__u8 lum_point[SHP_LUM_POINT_SIZE];
__u8 pbf_sigma[SHP_SIGMA_SIZE];
__u8 lum_clp_m[SHP_LUM_CLP_SIZE];
__s8 lum_min_m[SHP_LUM_MIN_SIZE];
__u8 mbf_sigma[SHP_SIGMA_SIZE];
__u8 lum_clp_h[SHP_LUM_CLP_SIZE];
__u8 hbf_sigma[SHP_SIGMA_SIZE];
__u8 edge_lum_thed[SHP_EDGE_LUM_THED_SIZE];
__u8 clamp_pos[SHP_CLAMP_SIZE];
__u8 clamp_neg[SHP_CLAMP_SIZE];
__u8 detail_alpha[SHP_DETAIL_ALPHA_SIZE];
u16 hbf_ratio __attribute__((aligned(2)));
u16 smoth_th4;
u16 l_alpha;
u16 g_alpha;
u16 rfl_ratio;
u16 rfh_ratio;
__u16 hbf_ratio __attribute__((aligned(2)));
__u16 smoth_th4;
__u16 l_alpha;
__u16 g_alpha;
__u16 rfl_ratio;
__u16 rfh_ratio;
} __attribute__ ((packed));
enum rkispp_fecbuf_stat {
@@ -289,43 +289,43 @@ enum rkispp_fecbuf_stat {
};
struct rkispp_fecbuf_info {
s32 buf_fd[FEC_MESH_BUF_MAX];
u32 buf_size[FEC_MESH_BUF_MAX];
__s32 buf_fd[FEC_MESH_BUF_MAX];
__u32 buf_size[FEC_MESH_BUF_MAX];
} __attribute__ ((packed));
struct rkispp_fecbuf_size {
u32 meas_width;
u32 meas_height;
u32 meas_mode;
__u32 meas_width;
__u32 meas_height;
__u32 meas_mode;
int buf_cnt;
} __attribute__ ((packed));
struct rkispp_fec_head {
enum rkispp_fecbuf_stat stat;
u32 meshxf_oft;
u32 meshyf_oft;
u32 meshxi_oft;
u32 meshyi_oft;
__u32 meshxf_oft;
__u32 meshyf_oft;
__u32 meshxi_oft;
__u32 meshyi_oft;
} __attribute__ ((packed));
struct rkispp_fec_config {
u8 mesh_density;
u8 crop_en;
u16 crop_width __attribute__((aligned(2)));
u16 crop_height;
u32 mesh_size __attribute__((aligned(4)));
s32 buf_fd;
__u8 mesh_density;
__u8 crop_en;
__u16 crop_width __attribute__((aligned(2)));
__u16 crop_height;
__u32 mesh_size __attribute__((aligned(4)));
__s32 buf_fd;
} __attribute__ ((packed));
struct rkispp_orb_config {
u8 limit_value;
u32 max_feature __attribute__((aligned(4)));
__u8 limit_value;
__u32 max_feature __attribute__((aligned(4)));
} __attribute__ ((packed));
struct rkispp_buf_info {
//s32 fd;
u32 index;
u32 size;
/* __s32 fd; */
__u32 index;
__u32 size;
} __attribute__ ((packed));
/**
@@ -337,11 +337,11 @@ struct rkispp_buf_info {
* @module_cfg_update: mask the config bits of which module should be updated
*/
struct rkispp_params_cfghead {
u32 module_en_update;
u32 module_ens;
u32 module_cfg_update;
__u32 module_en_update;
__u32 module_ens;
__u32 module_cfg_update;
u32 frame_id;
__u32 frame_id;
} __attribute__ ((packed));
/**
@@ -351,8 +351,8 @@ struct rkispp_params_tnrcfg {
struct rkispp_params_cfghead head;
struct rkispp_tnr_config tnr_cfg;
//struct rkispp_buf_info gain;
//struct rkispp_buf_info image;
/* struct rkispp_buf_info gain; */
/* struct rkispp_buf_info image; */
} __attribute__ ((packed));
/**
@@ -366,7 +366,7 @@ struct rkispp_params_nrcfg {
struct rkispp_orb_config orb_cfg;
struct rkispp_buf_info gain;
//struct rkispp_buf_info image;
/* struct rkispp_buf_info image; */
} __attribute__ ((packed));
/**
@@ -380,11 +380,11 @@ struct rkispp_params_feccfg {
} __attribute__ ((packed));
struct rkispp_orb_data {
u8 brief[ORB_BRIEF_NUM];
u32 y : 13;
u32 x : 13;
u32 dmy1 : 6;
u8 dmy2[ORB_DUMMY_NUM];
__u8 brief[ORB_BRIEF_NUM];
__u32 y : 13;
__u32 x : 13;
__u32 dmy1 : 6;
__u8 dmy2[ORB_DUMMY_NUM];
} __attribute__ ((packed));
/**
@@ -397,9 +397,9 @@ struct rkispp_orb_data {
struct rkispp_stats_nrbuf {
struct rkispp_orb_data data[ORB_DATA_NUM];
u32 total_num __attribute__((aligned(4)));
u32 meas_type;
u32 frame_id;
__u32 total_num __attribute__((aligned(4)));
__u32 meas_type;
__u32 frame_id;
struct rkispp_buf_info image;
} __attribute__ ((packed));
@@ -411,12 +411,12 @@ struct rkispp_stats_nrbuf {
* @frame_id: frame ID for sync
*/
struct rkispp_stats_tnrbuf {
u32 meas_type;
u32 frame_id;
__u32 meas_type;
__u32 frame_id;
struct rkispp_buf_info gain;
struct rkispp_buf_info gainkg;
//struct rkispp_buf_info image;
/* struct rkispp_buf_info image; */
} __attribute__ ((packed));
#endif

22
include/uapi/linux/rk-pcie-ep.h
View File

@@ -8,6 +8,22 @@
#include <linux/types.h>
/* rkep device mode status definition */
#define RKEP_MODE_BOOTROM 1
#define RKEP_MODE_LOADER 2
#define RKEP_MODE_KERNEL 3
#define RKEP_MODE_FUN0 4
/* Common status */
#define RKEP_SMODE_INIT 0
#define RKEP_SMODE_LNKRDY 1
#define RKEP_SMODE_LNKUP 2
#define RKEP_SMODE_ERR 0xff
/* Firmware download status */
#define RKEP_SMODE_FWDLRDY 0x10
#define RKEP_SMODE_FWDLDONE 0x11
/* Application status*/
#define RKEP_SMODE_APPRDY 0x20
/*
* rockchip pcie driver elbi ioctrl output data
*/
@@ -52,7 +68,11 @@ enum pcie_ep_mmap_resource {
struct pcie_ep_obj_info {
__u32 magic;
__u32 version;
__u8 reserved[0x1F8];
struct {
__u16 mode;
__u16 submode;
} devmode;
__u8 reserved[0x1F4];
__u32 irq_type_rc; /* Generate in ep isr, valid only for rc, clear in rc */
struct pcie_ep_obj_irq_dma_status dma_status_rc; /* Generate in ep isr, valid only for rc, clear in rc */

20
include/uapi/linux/rk-preisp.h
View File

@@ -48,23 +48,23 @@
#define PREISP_POWER_ON _IO('p', 1)
#define PREISP_POWER_OFF _IO('p', 2)
#define PREISP_REQUEST_SLEEP _IOW('p', 3, s32)
#define PREISP_REQUEST_SLEEP _IOW('p', 3, __s32)
#define PREISP_WAKEUP _IO('p', 4)
#define PREISP_DOWNLOAD_FW _IOW('p', 5, char[PREISP_FW_NAME_LEN])
#define PREISP_WRITE _IOW('p', 6, struct preisp_apb_pkt)
#define PREISP_READ _IOR('p', 7, struct preisp_apb_pkt)
#define PREISP_ST_QUERY _IOR('p', 8, s32)
#define PREISP_IRQ_REQUEST _IOW('p', 9, s32)
#define PREISP_SEND_MSG _IOW('p', 11, s32)
#define PREISP_QUERY_MSG _IOR('p', 12, s32)
#define PREISP_RECV_MSG _IOR('p', 13, s32)
#define PREISP_CLIENT_CONNECT _IOW('p', 15, s32)
#define PREISP_ST_QUERY _IOR('p', 8, __s32)
#define PREISP_IRQ_REQUEST _IOW('p', 9, __s32)
#define PREISP_SEND_MSG _IOW('p', 11, __s32)
#define PREISP_QUERY_MSG _IOR('p', 12, __s32)
#define PREISP_RECV_MSG _IOR('p', 13, __s32)
#define PREISP_CLIENT_CONNECT _IOW('p', 15, __s32)
#define PREISP_CLIENT_DISCONNECT _IO('p', 16)
struct preisp_apb_pkt {
s32 data_len;
s32 addr;
s32 *data;
__s32 data_len;
__s32 addr;
__s32 *data;
};
/**

2
include/uapi/linux/rk-video-format.h
View File

@@ -5,6 +5,8 @@
#ifndef _UAPI_RK_VIDEO_FORMAT_H
#define _UAPI_RK_VIDEO_FORMAT_H
#include <linux/types.h>
/* Four-character-code (FOURCC) */
#define v4l2_fourcc(a, b, c, d)\
((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))

34
include/uapi/linux/rk_vcm_head.h
View File

@@ -4,6 +4,9 @@
#ifndef RK_VCM_HEAD_H
#define RK_VCM_HEAD_H
#include <linux/types.h>
#include <linux/time_types.h>
#define RK_VCM_HEAD_VERSION KERNEL_VERSION(0, 0x02, 0x0)
/*
* Focus position values:
@@ -85,25 +88,25 @@
_IOR('V', BASE_VIDIOC_PRIVATE + 11, struct rk_cam_compat_vcm_tim)
struct rk_cam_modify_pos {
s32 focus_pos;
s32 zoom_pos;
s32 zoom1_pos;
__s32 focus_pos;
__s32 zoom_pos;
__s32 zoom1_pos;
};
struct rk_cam_set_focus {
bool is_need_reback;
s32 focus_pos;
_Bool is_need_reback;
__s32 focus_pos;
};
struct rk_cam_zoom_pos {
s32 zoom_pos;
s32 focus_pos;
__s32 zoom_pos;
__s32 focus_pos;
};
struct rk_cam_set_zoom {
bool is_need_zoom_reback;
bool is_need_focus_reback;
u32 setzoom_cnt;
_Bool is_need_zoom_reback;
_Bool is_need_focus_reback;
__u32 setzoom_cnt;
struct rk_cam_zoom_pos zoom_pos[VCMDRV_SETZOOM_MAXCNT];
};
@@ -112,9 +115,16 @@ struct rk_cam_vcm_tim {
struct __kernel_old_timeval vcm_end_t;
};
#ifndef __kernel_old_timeval32
struct __kernel_old_timeval32 {
__s32 tv_sec;
__s32 tv_usec;
};
#endif
struct rk_cam_compat_vcm_tim {
struct old_timeval32 vcm_start_t;
struct old_timeval32 vcm_end_t;
struct __kernel_old_timeval32 vcm_start_t;
struct __kernel_old_timeval32 vcm_end_t;
};
struct rk_cam_vcm_cfg {

8
include/uapi/linux/rkcif-config.h
View File

@@ -60,10 +60,10 @@ enum cif_csi_lvds_memory {
*/
struct bayer_blc {
u8 pattern00;
u8 pattern01;
u8 pattern02;
u8 pattern03;
__u8 pattern00;
__u8 pattern01;
__u8 pattern02;
__u8 pattern03;
};
struct rkcif_fps {

4
include/uapi/misc/dw_hdcp2.h
View File

@@ -12,7 +12,7 @@
#include <linux/types.h>
#define HL_DRIVER_ALLOCATE_DYNAMIC_MEM 0xffffffff
// hl_drv_ioctl numbers
/* hl_drv_ioctl numbers */
enum {
HL_DRV_NR_MIN = 0x10,
HL_DRV_NR_INIT,
@@ -127,4 +127,4 @@ struct hl_drv_ioc_status {
#define RK_DRV_IOC_RESET _IOR('H', RK_DRV_NR_RESET, __u32)
#endif // _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_
#endif /* _DW_HDCP_HOST_LIB_DRIVER_LINUX_IF_H_ */

7
include/uapi/misc/rkflash_vendor_storage.h
View File

@@ -1,12 +1,13 @@
/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */
/* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd */
#include <linux/ioctl.h>
/* Copyright (c) 2023 Rockchip Electronics Co., Ltd */
#ifndef _RKFLASH_VENDOR_STORAGE
#define _RKFLASH_VENDOR_STORAGE
#include <linux/types.h>
#include <linux/ioctl.h>
struct RK_VENDOR_REQ {
__u32 tag;
__u16 id;