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UPSTREAM: ARM: 9268/1: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16
Floating point half-precision (FPHP) and Advanced SIMD half-precision
(ASIMDHP) are VFP features (FEAT_FP16) represented by MVFR1 identification register. These capabilities can optionally exist with VFPv3 and mandatory with VFPv4. Both these new features exist for Armv8 architecture in AArch32 state.
These hwcaps may be useful for the userspace to add conditional check
before trying to use FEAT_FP16 feature specific instructions.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Bug: 282663915
(cherry picked from commit c00a19c8b1)
Change-Id: I46af49d39168b0d35db05cdd1499f9b7df030f09
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
This commit is contained in:
committed by
Todd Kjos
parent
52e28a12a9
commit
49c6c1e40f
@@ -87,6 +87,12 @@
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#define MVFR0_DP_BIT (8)
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#define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT)
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/* MVFR1 bits */
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#define MVFR1_ASIMDHP_BIT (20)
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#define MVFR1_ASIMDHP_MASK (0xf << MVFR1_ASIMDHP_BIT)
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#define MVFR1_FPHP_BIT (24)
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#define MVFR1_FPHP_MASK (0xf << MVFR1_FPHP_BIT)
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/* Bit patterns for decoding the packaged operation descriptors */
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#define VFPOPDESC_LENGTH_BIT (9)
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#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
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@@ -28,6 +28,8 @@
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#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
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#define HWCAP_LPAE (1 << 20)
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#define HWCAP_EVTSTRM (1 << 21)
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#define HWCAP_FPHP (1 << 22)
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#define HWCAP_ASIMDHP (1 << 23)
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/*
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* HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
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@@ -1248,6 +1248,8 @@ static const char *hwcap_str[] = {
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"vfpd32",
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"lpae",
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"evtstrm",
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"fphp",
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"asimdhp",
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NULL
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};
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@@ -831,6 +831,10 @@ static int __init vfp_init(void)
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if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
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elf_hwcap |= HWCAP_VFPv4;
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if (((fmrx(MVFR1) & MVFR1_ASIMDHP_MASK) >> MVFR1_ASIMDHP_BIT) == 0x2)
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elf_hwcap |= HWCAP_ASIMDHP;
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if (((fmrx(MVFR1) & MVFR1_FPHP_MASK) >> MVFR1_FPHP_BIT) == 0x3)
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elf_hwcap |= HWCAP_FPHP;
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}
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/* Extract the architecture version on pre-cpuid scheme */
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} else {
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