From 4a1351fd46b689335f4871c4eea38f7cf3f8d56e Mon Sep 17 00:00:00 2001
From: Jianqun Xu <jay.xu@rock-chips.com>
Date: Fri, 1 Mar 2019 14:22:23 +0800
Subject: [PATCH] Revert "ARM64: dts: rk3399: assign clk parent and rate for
 SCLK_EMMC"

This reverts commit e944f546851bd90d0dc2ad914ab8548cb0be00a1.
According to:
commit 44c69f1dc01c3e073d515073066029fcdd39e7fe
Author: xiaoyao <xiaoyao@rock-chips.com>
Date:   Thu Sep 22 17:33:47 2016 +0800

    UPSTREAM: ARM64: dts: rockchip: update rk3399.dtsi for emmc&phy

    Change-Id: I97948c250f63423c5a7f305cfaa3a10b190f736f
    Signed-off-by: xiaoyao <xiaoyao@rock-chips.com>

Change-Id: I94ab7db285acfaa71f923b455dc4aad8773c159f
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4bd0ad9d8750..b0d82fe9b747 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -373,7 +373,6 @@
 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 		arasan,soc-ctl-syscon = <&grf>;
 		assigned-clocks = <&cru SCLK_EMMC>;
-		assigned-clock-parents = <&cru PLL_CPLL>;
 		assigned-clock-rates = <200000000>;
 		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 		clock-names = "clk_xin", "clk_ahb";