From 4a67123cc773fac29e1dc848e7b6014517365ba2 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Sun, 18 Mar 2018 21:41:43 +0800 Subject: [PATCH] clk: rockchip: rk3228: Fix sclk_wifi div_width Change-Id: I8e216249fbd588ce55660eba9911fc59aedc920d Signed-off-by: Finley Xiao Signed-off-by: Elaine Zhang --- drivers/clk/rockchip/clk-rk3228.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c index d77e1d94643b..59880c2aba36 100644 --- a/drivers/clk/rockchip/clk-rk3228.c +++ b/drivers/clk/rockchip/clk-rk3228.c @@ -178,7 +178,7 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = { [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), RK2928_MODE_CON, 8, 8, 0, NULL), [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9), - RK2928_MODE_CON, 12, 9, ROCKCHIP_PLL_SYNC_RATE, rk3228_pll_rates), + RK2928_MODE_CON, 12, 9, 0, rk3228_pll_rates), }; #define MFLAGS CLK_MUX_HIWORD_MASK @@ -361,7 +361,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = { RK2928_CLKGATE_CON(10), 12, GFLAGS), COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0, - RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 5, DFLAGS, RK2928_CLKGATE_CON(2), 15, GFLAGS), COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,