From 4adb1baf9127d7018d3ffde8dae36d8cb49882ae Mon Sep 17 00:00:00 2001 From: Algea Cao Date: Sat, 22 Jan 2022 18:37:20 +0800 Subject: [PATCH] drm/rockchip: vop2: Don't check mode valid when use hdmiphy-pll Signed-off-by: Algea Cao Change-Id: I23d5d097ff35d818021eaa09dd6af0e9906c6b4d --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index c970b9af2002..1d2b8656d9f5 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -5157,10 +5157,15 @@ vop2_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode) if (mode->flags & DRM_MODE_FLAG_DBLCLK) request_clock *= 2; - if (request_clock <= VOP2_MAX_DCLK_RATE) - clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000; - else + if (request_clock <= VOP2_MAX_DCLK_RATE) { + if (vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll") || + vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll")) + clock = request_clock; + else + clock = clk_round_rate(vp->dclk, request_clock * 1000) / 1000; + } else { clock = request_clock; + } /* * Hdmi or DisplayPort request a Accurate clock.