From 4ae0b40f643f64b3cd42d5619db5b37d4fd0c6df Mon Sep 17 00:00:00 2001 From: William Wu Date: Tue, 24 Nov 2020 15:18:02 +0800 Subject: [PATCH] dt-bindings: phy-rockchip-naneng-combphy: add property to disable u3 port This patch add new property to disable u3 root port for usb3.0 controller if we want to force the controller to u2 only mode. Change-Id: I53da3a7816585f1d3f9ac7fd3ee5ba8ba323eff1 Signed-off-by: William Wu --- .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.txt b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.txt index 59fa795c431c..48ffd50efa9d 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.txt @@ -17,6 +17,8 @@ Optional properties: - assigned-clock-parents : parent of clk_xxx_osc or clk_xxx_div. Refer to clk/clock-bindings.txt for generic clock consumer properties. + - rockchip,dis-u3otg0-port: when set, disable the u3 root port of otg0 host. + - rockchip,dis-u3otg1-port: when set, disable the u3 root port of otg1 host. Example: