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add scu.h

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黄涛
2010-05-11 01:21:23 +00:00
parent 0d43be70bd
commit 4b5d517f8a
2 changed files with 123 additions and 92 deletions
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111
arch/arm/mach-rk2818/clock.c
View File

@@ -25,77 +25,7 @@
#include <linux/version.h>
#include <asm/clkdev.h>
#include <mach/rk2818_iomap.h>
enum
{
/* SCU CLK GATE 0 CON */
SCU_IPID_ARM = 0,
SCU_IPID_DSP,
SCU_IPID_DMA,
SCU_IPID_SRAMARM,
SCU_IPID_SRAMDSP,
SCU_IPID_HIF,
SCU_IPID_OTGBUS,
SCU_IPID_OTGPHY,
SCU_IPID_NANDC,
SCU_IPID_INTC,
SCU_IPID_DEBLK, /* 10 */
SCU_IPID_LCDC,
SCU_IPID_VIP, /* as sensor */
SCU_IPID_I2S,
SCU_IPID_SDMMC0, /* 14 */
SCU_IPID_EBROM,
SCU_IPID_GPIO0,
SCU_IPID_GPIO1,
SCU_IPID_UART0,
SCU_IPID_UART1,
SCU_IPID_I2C0, /* 20 */
SCU_IPID_I2C1,
SCU_IPID_SPI0,
SCU_IPID_SPI1,
SCU_IPID_PWM,
SCU_IPID_TIMER,
SCU_IPID_WDT,
SCU_IPID_RTC,
SCU_IPID_LSADC,
SCU_IPID_UART2,
SCU_IPID_UART3, /* 30 */
SCU_IPID_SDMMC1,
/* SCU CLK GATE 1 CON */
SCU_IPID_HSADC = 32,
SCU_IPID_MOBILE_SDARM_COMMON = 47,
SCU_IPID_SDRAM_CONTROLLER,
SCU_IPID_MOBILE_SDRAM_CONTROLLER,
SCU_IPID_LCDC_SHARE_MEMORY, /* 50 */
SCU_IPID_LCDC_HCLK,
SCU_IPID_DEBLK_H264,
SCU_IPID_GPU,
SCU_IPID_DDR_HCLK,
SCU_IPID_DDR,
SCU_IPID_CUSTOMIZED_SDRAM_CONTROLLER,
SCU_IPID_MCDMA,
SCU_IPID_SDRAM,
SCU_IPID_DDR_AXI,
SCU_IPID_DSP_TIMER, /* 60 */
SCU_IPID_DSP_SLAVE,
SCU_IPID_DSP_MASTER,
SCU_IPID_USB_HOST,
/* SCU CLK GATE 2 CON */
SCU_IPID_ARMIBUS = 64,
SCU_IPID_ARMDBUS,
SCU_IPID_DSPBUS,
SCU_IPID_EXPBUS,
SCU_IPID_APBBUS,
SCU_IPID_EFUSE,
SCU_IPID_DTCM1, /* 70 */
SCU_IPID_DTCM0,
SCU_IPID_ITCM,
SCU_IPID_VIDEOBUS,
SCU_IPID_GATE_MAX,
};
#include <mach/scu.h>
static struct rockchip_scu_reg_hw
{
@@ -113,9 +43,9 @@ static struct rockchip_scu_reg_hw
u32 scu_clksel2_config;
} *scu_register_base = (struct rockchip_scu_reg_hw *)(RK2818_SCU_BASE);
#define CLKSEL0_REG (u32 __iomem *)(RK2818_SCU_BASE + 0x14)
#define CLKSEL1_REG (u32 __iomem *)(RK2818_SCU_BASE + 0x18)
#define CLKSEL2_REG (u32 __iomem *)(RK2818_SCU_BASE + 0x34)
#define CLKSEL0_REG (u32 __iomem *)SCU_CLKSEL0_CON
#define CLKSEL1_REG (u32 __iomem *)SCU_CLKSEL1_CON
#define CLKSEL2_REG (u32 __iomem *)SCU_CLKSEL2_CON
/* SCU PLL CON */
#define PLL_TEST (0x01u<<25)
@@ -218,9 +148,6 @@ struct clk {
u32 clksel_mask;
u8 clksel_shift;
u8 clksel_maxdiv;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */
#endif
};
static void __clk_disable(struct clk *clk);
@@ -722,7 +649,7 @@ static int gate_mode(struct clk *clk, int on)
int idx = clk->gate_idx;
u32 v;
if (idx >= SCU_IPID_GATE_MAX)
if (idx >= CLK_GATE_MAX)
return -EINVAL;
reg = &scu_register_base->scu_clkgate0_config;
@@ -770,7 +697,7 @@ static struct clk uart##n##_clk = { \
.recalc = followparent_recalc, \
.get_parent = uart_clk_get_parent, \
.set_parent = uart_clk_set_parent, \
.gate_idx = SCU_IPID_UART##n, \
.gate_idx = CLK_GATE_UART##n, \
}
#define GATE_CLK(NAME,PARENT,ID) \
@@ -779,7 +706,7 @@ static struct clk NAME##_clk = { \
.parent = &PARENT, \
.mode = gate_mode, \
.recalc = followparent_recalc, \
.gate_idx = SCU_IPID_##ID, \
.gate_idx = CLK_GATE_##ID, \
}
GATE_CLK(arm_core, arm_clk, ARM);
@@ -796,7 +723,7 @@ static struct clk otgphy_clk = {
.recalc = followparent_recalc,
.get_parent = otgphy_clk_get_parent,
.set_parent = otgphy_clk_set_parent,
.gate_idx = SCU_IPID_OTGPHY,
.gate_idx = CLK_GATE_OTGPHY,
};
GATE_CLK(nandc, arm_hclk, NANDC);
GATE_CLK(intc, arm_hclk, INTC);
@@ -808,7 +735,7 @@ static struct clk lcdc_clk = {
.recalc = followparent_recalc,
.get_parent = lcdc_clk_get_parent,
.set_parent = lcdc_clk_set_parent,
.gate_idx = SCU_IPID_LCDC,
.gate_idx = CLK_GATE_LCDC,
};
static struct clk vip_clk = {
.name = "vip",
@@ -817,7 +744,7 @@ static struct clk vip_clk = {
.recalc = followparent_recalc,
.get_parent = vip_clk_get_parent,
.set_parent = vip_clk_set_parent,
.gate_idx = SCU_IPID_VIP,
.gate_idx = CLK_GATE_VIP,
};
static struct clk i2s_clk = {
.name = "i2s",
@@ -826,7 +753,7 @@ static struct clk i2s_clk = {
.recalc = followparent_recalc,
.get_parent = i2s_clk_get_parent,
.set_parent = i2s_clk_set_parent,
.gate_idx = SCU_IPID_I2S,
.gate_idx = CLK_GATE_I2S,
};
static struct clk sdmmc0_clk = {
.name = "sdmmc0",
@@ -834,7 +761,7 @@ static struct clk sdmmc0_clk = {
.mode = gate_mode,
.recalc = clksel_recalc,
.set_rate = clksel_set_rate,
.gate_idx = SCU_IPID_SDMMC0,
.gate_idx = CLK_GATE_SDMMC0,
.clksel_reg = CLKSEL0_REG,
.clksel_mask = 7 << 4,
.clksel_shift = 4,
@@ -860,7 +787,7 @@ static struct clk lsadc_clk = {
.mode = gate_mode,
.recalc = clksel_recalc,
.set_rate = clksel_set_rate,
.gate_idx = SCU_IPID_LSADC,
.gate_idx = CLK_GATE_LSADC,
.clksel_reg = CLKSEL1_REG,
.clksel_mask = 0xFF << 8,
.clksel_shift = 8,
@@ -874,7 +801,7 @@ static struct clk sdmmc1_clk = {
.mode = gate_mode,
.recalc = clksel_recalc,
.set_rate = clksel_set_rate,
.gate_idx = SCU_IPID_SDMMC1,
.gate_idx = CLK_GATE_SDMMC1,
.clksel_reg = CLKSEL2_REG,
.clksel_mask = 7 << 8,
.clksel_shift = 8,
@@ -891,9 +818,9 @@ static struct clk hsadc_clk = {
.parent = &demod_clk,
.mode = gate_mode,
.recalc = hsadc_clk_recalc,
.gate_idx = SCU_IPID_HSADC,
.gate_idx = CLK_GATE_HSADC,
};
GATE_CLK(mobile_sdram_common, arm_hclk, MOBILE_SDARM_COMMON);
GATE_CLK(sdram_common, arm_hclk, SDRAM_COMMON);
GATE_CLK(sdram_controller, arm_hclk, SDRAM_CONTROLLER);
GATE_CLK(mobile_sdram_controller, arm_hclk, MOBILE_SDRAM_CONTROLLER);
GATE_CLK(lcdc_share_memory, arm_hclk, LCDC_SHARE_MEMORY);
@@ -909,7 +836,7 @@ static struct clk ddr_clk = {
.set_rate = clksel_set_rate_shift,
.get_parent = ddr_clk_get_parent,
.set_parent = ddr_clk_set_parent,
.gate_idx = SCU_IPID_DDR,
.gate_idx = CLK_GATE_DDR,
.clksel_reg = CLKSEL0_REG,
.clksel_mask = 0x3 << 30,
.clksel_shift = 30,
@@ -1000,7 +927,7 @@ static struct clk_lookup clks[] = {
CLK1(sdmmc1),
CLK1(hsadc),
CLK1(mobile_sdram_common),
CLK1(sdram_common),
CLK1(sdram_controller),
CLK1(mobile_sdram_controller),
CLK1(lcdc_share_memory),
@@ -1407,7 +1334,7 @@ static void dump_clock(struct seq_file *s, struct clk *clk, int deep)
seq_printf(s, "%-9s ", clk->name);
if (clk->gate_idx < SCU_IPID_GATE_MAX) {
if (clk->gate_idx < CLK_GATE_MAX) {
u32 *reg;
int idx = clk->gate_idx;
u32 v;

104
arch/arm/mach-rk2818/include/mach/scu.h Normal file
View File

@@ -0,0 +1,104 @@
/* arch/arm/mach-rk2818/include/mach/scu.h
*
* Copyright (C) 2010 ROCKCHIP, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ASM_ARCH_RK2818_SCU_H
enum scu_clk_gate
{
/* SCU CLK GATE 0 CON */
CLK_GATE_ARM = 0,
CLK_GATE_DSP,
CLK_GATE_DMA,
CLK_GATE_SRAMARM,
CLK_GATE_SRAMDSP,
CLK_GATE_HIF,
CLK_GATE_OTGBUS,
CLK_GATE_OTGPHY,
CLK_GATE_NANDC,
CLK_GATE_INTC,
CLK_GATE_DEBLK, /* 10 */
CLK_GATE_LCDC,
CLK_GATE_VIP, /* as sensor */
CLK_GATE_I2S,
CLK_GATE_SDMMC0,
CLK_GATE_EBROM,
CLK_GATE_GPIO0,
CLK_GATE_GPIO1,
CLK_GATE_UART0,
CLK_GATE_UART1,
CLK_GATE_I2C0, /* 20 */
CLK_GATE_I2C1,
CLK_GATE_SPI0,
CLK_GATE_SPI1,
CLK_GATE_PWM,
CLK_GATE_TIMER,
CLK_GATE_WDT,
CLK_GATE_RTC,
CLK_GATE_LSADC,
CLK_GATE_UART2,
CLK_GATE_UART3, /* 30 */
CLK_GATE_SDMMC1,
/* SCU CLK GATE 1 CON */
CLK_GATE_HSADC = 32,
CLK_GATE_SDRAM_COMMON = 47,
CLK_GATE_SDRAM_CONTROLLER,
CLK_GATE_MOBILE_SDRAM_CONTROLLER,
CLK_GATE_LCDC_SHARE_MEMORY, /* 50 */
CLK_GATE_LCDC_HCLK,
CLK_GATE_DEBLK_H264,
CLK_GATE_GPU,
CLK_GATE_DDR_HCLK,
CLK_GATE_DDR,
CLK_GATE_CUSTOMIZED_SDRAM_CONTROLLER,
CLK_GATE_MCDMA,
CLK_GATE_SDRAM,
CLK_GATE_DDR_AXI,
CLK_GATE_DSP_TIMER, /* 60 */
CLK_GATE_DSP_SLAVE,
CLK_GATE_DSP_MASTER,
CLK_GATE_USB_HOST,
/* SCU CLK GATE 2 CON */
CLK_GATE_ARMIBUS = 64,
CLK_GATE_ARMDBUS,
CLK_GATE_DSPBUS,
CLK_GATE_EXPBUS,
CLK_GATE_APBBUS,
CLK_GATE_EFUSE,
CLK_GATE_DTCM1, /* 70 */
CLK_GATE_DTCM0,
CLK_GATE_ITCM,
CLK_GATE_VIDEOBUS,
CLK_GATE_MAX,
};
#define SCU_APLL_CON (RK2818_SCU_BASE + 0x00)
#define SCU_DPLL_CON (RK2818_SCU_BASE + 0x04)
#define SCU_CPLL_CON (RK2818_SCU_BASE + 0x08)
#define SCU_MODE_CON (RK2818_SCU_BASE + 0x0c)
#define SCU_PMU_CON (RK2818_SCU_BASE + 0x10)
#define SCU_CLKSEL0_CON (RK2818_SCU_BASE + 0x14)
#define SCU_CLKSEL1_CON (RK2818_SCU_BASE + 0x18)
#define SCU_CLKGATE0_CON (RK2818_SCU_BASE + 0x1c)
#define SCU_CLKGATE1_CON (RK2818_SCU_BASE + 0x20)
#define SCU_CLKGATE2_CON (RK2818_SCU_BASE + 0x24)
#define SCU_SOFTRST_CON (RK2818_SCU_BASE + 0x28)
#define SCU_CHIPCFG_CON (RK2818_SCU_BASE + 0x2c)
#define SCU_CPUPD (RK2818_SCU_BASE + 0x30)
#define SCU_CLKSEL2_CON (RK2818_SCU_BASE + 0x34)
#endif