From 4bc9aff1c86cd9ec01dc808a7b27b45de5a10ed1 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Thu, 21 Mar 2019 09:22:37 +0800 Subject: [PATCH] pinctrl: rockchip: add calculate slew rate for rk1808 Change-Id: Ia78e6ceda688942b655623d80fe4fe9fc1b349cc Signed-off-by: Jianqun Xu --- drivers/pinctrl/pinctrl-rockchip.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 523d72d3073f..6a7a11e488bd 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2076,6 +2076,32 @@ rk1808_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, return DRV_TYPE_IO_DEFAULT; } +#define RK1808_SR_PMU_OFFSET 0x0030 +#define RK1808_SR_GRF_OFFSET 0x00c0 +#define RK1808_SR_BANK_STRIDE 16 +#define RK1808_SR_PINS_PER_REG 8 + +static int rk1808_calc_slew_rate_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl *info = bank->drvdata; + + if (bank->bank_num == 0) { + *regmap = info->regmap_pmu; + *reg = RK1808_SR_PMU_OFFSET; + } else { + *regmap = info->regmap_base; + *reg = RK1808_SR_GRF_OFFSET; + *reg += (bank->bank_num - 1) * RK1808_SR_BANK_STRIDE; + } + *reg += ((pin_num / RK1808_SR_PINS_PER_REG) * 4); + *bit = pin_num % RK1808_SR_PINS_PER_REG; + + return 0; +} + #define RK1808_SCHMITT_PMU_OFFSET 0x0040 #define RK1808_SCHMITT_GRF_OFFSET 0x0100 #define RK1808_SCHMITT_BANK_STRIDE 16 @@ -4698,6 +4724,7 @@ static struct rockchip_pin_ctrl rk1808_pin_ctrl = { .pull_calc_reg = rk1808_calc_pull_reg_and_bit, .drv_calc_reg = rk1808_calc_drv_reg_and_bit, .schmitt_calc_reg = rk1808_calc_schmitt_reg_and_bit, + .slew_rate_calc_reg = rk1808_calc_slew_rate_reg_and_bit, }; static struct rockchip_pin_bank rk2928_pin_banks[] = {