From 4bf28537d2d89ca146977332b1452e413f5b1c5c Mon Sep 17 00:00:00 2001
From: Hu Kejun <william.hu@rock-chips.com>
Date: Tue, 9 Oct 2018 20:02:41 +0800
Subject: [PATCH] arm64: dts: rockchip: rk1808: add dts of rkisp1

Change-Id: Ida396c224318e1ad223782ef5becc830521d86be
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk1808.dtsi | 44 ++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index a5a368dec70c..b521d10bb621 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -396,6 +396,16 @@
 			<100000000>;
 	};
 
+	mipi_dphy_rx: mipi-dphy-rx@ff360000 {
+		compatible = "rockchip,rk1808-mipi-dphy-rx";
+		reg = <0x0 0xff360000 0x0 0x4000>;
+		clocks = <&cru PCLK_MIPICSIPHY>;
+		clock-names = "pclk";
+		power-domains = <&power RK1808_PD_VIO>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+	};
+
 	mipi_dphy: mipi-dphy@ff370000 {
 		compatible = "rockchip,rk1808-mipi-dphy";
 		reg = <0x0 0xff370000 0x0 0x500>;
@@ -1138,6 +1148,33 @@
 		status = "disabled";
 	};
 
+	rkisp1: rkisp1@ffb50000 {
+		compatible = "rockchip,rk1808-rkisp1";
+		reg = <0x0 0xffb50000 0x0 0x8000>;
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
+			<&cru SCLK_ISP>, <&cru DCLK_CIF>;
+		clock-names = "aclk_isp", "hclk_isp",
+			"clk_isp", "pclk_isp";
+		power-domains = <&power RK1808_PD_VIO>;
+		iommus = <&isp_mmu>;
+		status = "disabled";
+	};
+
+	isp_mmu: iommu@ffb58000 {
+		compatible = "rockchip,iommu";
+		reg = <0x0 0xffb58000 0x0 0x100>;
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_mmu";
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
+			<&cru SCLK_ISP>;
+		clock-names = "aclk", "hclk", "sclk";
+		power-domains = <&power RK1808_PD_VIO>;
+		rk_iommu,disable_reset_quirk;
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	vpu_service: vpu_service@ffb80000 {
 		compatible = "rockchip,vpu_service";
 		reg = <0x0 0xffb80000 0x0 0x800>;
@@ -1454,6 +1491,13 @@
 			input-schmitt-enable;
 		};
 
+		cif-m0 {
+			cif_clkout_m0: cif-clkout-m0 {
+				rockchip,pins =
+					<2 RK_PB7 1 &pcfg_pull_none>;
+			};
+		};
+
 		emmc {
 			emmc_clk: emmc-clk {
 				rockchip,pins =