From 4c221bf59dc3ba2c5d17e254e512e6a9ba31bc56 Mon Sep 17 00:00:00 2001
From: Cai YiWei <cyw@rock-chips.com>
Date: Sat, 8 Feb 2025 15:35:50 +0800
Subject: [PATCH] arm64: dts: rockchip: rv1126b: add isp node

Change-Id: Ie65077e1feaecb907d168561c075f3ec996fb6cc
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rv1126b.dtsi | 61 +++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
index c915c786ddc8..0b07d6373997 100644
--- a/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rv1126b.dtsi
@@ -340,6 +340,34 @@
 		status = "disabled";
 	};
 
+	rkisp_vir0: rkisp-vir0 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		dvbm = <&rkdvbm>;
+		status = "disabled";
+	};
+
+	rkisp_vir1: rkisp-vir1 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		dvbm = <&rkdvbm>;
+		status = "disabled";
+	};
+
+	rkisp_vir2: rkisp-vir2 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		dvbm = <&rkdvbm>;
+		status = "disabled";
+	};
+
+	rkisp_vir3: rkisp-vir3 {
+		compatible = "rockchip,rkisp-vir";
+		rockchip,hw = <&rkisp>;
+		dvbm = <&rkdvbm>;
+		status = "disabled";
+	};
+
 	thermal_zones: thermal-zones {
 		cpu_thermal: cpu-thermal {
 			polling-delay-passive = <20>; /* milliseconds */
@@ -939,6 +967,39 @@
 		status = "okay";
 	};
 
+	rkisp: isp@21d00000 {
+		compatible = "rockchip,rv1126b-rkisp";
+		reg = <0x21d00000 0x7f00>, <0x21d30000 0x2f00>;
+		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_mipi_irq", "isp_mi_irq", "isp_irq",
+				  "vpsl_mi_irq", "vpsl_irq";
+		clocks = <&cru HCLK_ISP>, <&cru ACLK_ISP>,
+			 <&cru CLK_CORE_ISP>, <&cru ISP0CLK_VICAP>,
+			 <&cru HCLK_VPSL>, <&cru ACLK_VPSL>, <&cru CLK_CORE_VPSL>;
+		clock-names = "hclk_isp", "aclk_isp",
+			      "clk_isp_core", "clk_isp_vicap",
+			      "hclk_vpsl", "aclk_vpsl", "clk_core_vpsl";
+		iommus = <&rkisp_mmu>;
+		status = "disabled";
+	};
+
+	rkisp_mmu: iommu@21d07f00 {
+		compatible = "rockchip,iommu-v2";
+		reg = <0x21d07f00 0x100>, <0x21d32f00 0x100>;
+		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "isp_mmu", "vpsl_mmu";
+		clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
+			 <&cru ACLK_VPSL>, <&cru HCLK_VPSL>;
+		clock-names = "aclk0", "iface0", "aclk1", "iface1";
+		#iommu-cells = <0>;
+		rockchip,disable-mmu-reset;
+		status = "disabled";
+	};
+
 	rkcif: rkcif@21d10000 {
 		compatible = "rockchip,rv1126b-cif";
 		reg = <0x21d10000 0x1000>;