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MALI: rockchip: upgrade bifrost DDK to g24p0-00eac0, from g22p0-01eac0

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mali_csffw.bin from Valhall DDK g24(r49) is included.

Change-Id: Ic48b63e744457163fbae3f41b477fc2827a1380e
Signed-off-by: Zhen Chen <chenzhen@rock-chips.com>
This commit is contained in:
Zhen Chen
2024-08-12 15:27:25 +08:00
committed by Tao Huang
parent f8fff854d7
commit 4cedc115fd
147 changed files with 5342 additions and 2886 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/uapi/gpu/arm/bifrost/backend/gpu/mali_kbase_model_dummy.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2021-2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2021-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software

49
include/uapi/gpu/arm/bifrost/csf/mali_base_csf_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -46,7 +46,11 @@
*/
#define BASE_MEM_CSF_EVENT ((base_mem_alloc_flags)1 << 19)
#define BASE_MEM_RESERVED_BIT_20 ((base_mem_alloc_flags)1 << 20)
/* Unused bit for CSF, only used in JM for BASE_MEM_TILER_ALIGN_TOP */
#define BASE_MEM_UNUSED_BIT_20 ((base_mem_alloc_flags)1 << 20)
/* Unused bit for CSF, only used in JM for BASE_MEM_FLAG_MAP_FIXED */
#define BASE_MEM_UNUSED_BIT_27 ((base_mem_alloc_flags)1 << 27)
/* Must be FIXABLE memory: its GPU VA will be determined at a later point,
* at which time it will be at a fixed GPU VA.
@@ -62,9 +66,14 @@
*/
#define BASEP_MEM_FLAGS_KERNEL_ONLY (BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE)
/* A mask of all currently reserved flags
*/
#define BASE_MEM_FLAGS_RESERVED BASE_MEM_RESERVED_BIT_20
/* A mask of all flags that should not be queried */
#define BASE_MEM_DONT_QUERY (BASE_MEM_COHERENT_SYSTEM_REQUIRED | BASE_MEM_IMPORT_SHARED)
/* A mask of all currently reserved flags */
#define BASE_MEM_FLAGS_RESERVED ((base_mem_alloc_flags)0)
/* A mask of all bits that are not used by a flag on CSF */
#define BASE_MEM_FLAGS_UNUSED (BASE_MEM_UNUSED_BIT_20 | BASE_MEM_UNUSED_BIT_27)
/* Special base mem handles specific to CSF.
*/
@@ -474,7 +483,26 @@ struct base_gpu_queue_error_fatal_payload {
};
/**
* enum base_gpu_queue_group_error_type - GPU Fatal error type.
* struct base_gpu_queue_error_fault_payload - Recoverable fault
* error information related to GPU command queue.
*
* @sideband: Additional information about this recoverable fault.
* @status: Recoverable fault information.
* This consists of exception type (least significant byte) and
* data (remaining bytes). One example of exception type is
* INSTR_INVALID_PC (0x50).
* @csi_index: Index of the CSF interface the queue is bound to.
* @padding: Padding to make multiple of 64bits
*/
struct base_gpu_queue_error_fault_payload {
__u64 sideband;
__u32 status;
__u8 csi_index;
__u8 padding[3];
};
/**
* enum base_gpu_queue_group_error_type - GPU error type.
*
* @BASE_GPU_QUEUE_GROUP_ERROR_FATAL: Fatal error associated with GPU
* command queue group.
@@ -484,7 +512,9 @@ struct base_gpu_queue_error_fatal_payload {
* progress timeout.
* @BASE_GPU_QUEUE_GROUP_ERROR_TILER_HEAP_OOM: Fatal error due to running out
* of tiler heap memory.
* @BASE_GPU_QUEUE_GROUP_ERROR_FATAL_COUNT: The number of fatal error types
* @BASE_GPU_QUEUE_GROUP_QUEUE_ERROR_FAULT: Fault error associated with GPU
* command queue.
* @BASE_GPU_QUEUE_GROUP_ERROR_FATAL_COUNT: The number of GPU error types
*
* This type is used for &struct_base_gpu_queue_group_error.error_type.
*/
@@ -493,6 +523,7 @@ enum base_gpu_queue_group_error_type {
BASE_GPU_QUEUE_GROUP_QUEUE_ERROR_FATAL,
BASE_GPU_QUEUE_GROUP_ERROR_TIMEOUT,
BASE_GPU_QUEUE_GROUP_ERROR_TILER_HEAP_OOM,
BASE_GPU_QUEUE_GROUP_QUEUE_ERROR_FAULT,
BASE_GPU_QUEUE_GROUP_ERROR_FATAL_COUNT
};
@@ -512,6 +543,7 @@ struct base_gpu_queue_group_error {
union {
struct base_gpu_queue_group_error_fatal_payload fatal_group;
struct base_gpu_queue_error_fatal_payload fatal_queue;
struct base_gpu_queue_error_fault_payload fault_queue;
} payload;
};
@@ -519,8 +551,7 @@ struct base_gpu_queue_group_error {
* enum base_csf_notification_type - Notification type
*
* @BASE_CSF_NOTIFICATION_EVENT: Notification with kernel event
* @BASE_CSF_NOTIFICATION_GPU_QUEUE_GROUP_ERROR: Notification with GPU fatal
* error
* @BASE_CSF_NOTIFICATION_GPU_QUEUE_GROUP_ERROR: Notification with GPU error
* @BASE_CSF_NOTIFICATION_CPU_QUEUE_DUMP: Notification with dumping cpu
* queue
* @BASE_CSF_NOTIFICATION_COUNT: The number of notification type

43
include/uapi/gpu/arm/bifrost/csf/mali_kbase_csf_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -95,15 +95,31 @@
* 1.22:
* - Add comp_pri_threshold and comp_pri_ratio attributes to
* kbase_ioctl_cs_queue_group_create.
* - Made the BASE_MEM_DONT_NEED memory flag queryable.
* 1.23:
* - Disallows changing the sharability on the GPU of imported dma-bufs to
* BASE_MEM_COHERENT_SYSTEM using KBASE_IOCTL_MEM_FLAGS_CHANGE.
* 1.24:
* - Implement full block state support for hardware counters.
* 1.25:
* - Add support for CS_FAULT reporting to userspace
* 1.26:
* - Made the BASE_MEM_IMPORT_SYNC_ON_MAP_UNMAP and BASE_MEM_KERNEL_SYNC memory
* flags queryable.
* 1.27:
* - Implement support for HWC block state availability.
* 1.28:
* - Made the SAME_VA memory flag queryable.
* 1.29:
* - Re-allow child process to do supported file operations (like mmap, ioctl
* read, poll) on the file descriptor of mali device that was inherited
* from the parent process.
* 1.30:
* - Implement support for setting GPU Timestamp Offset register.
*/
#define BASE_UK_VERSION_MAJOR 1
#define BASE_UK_VERSION_MINOR 24
#define BASE_UK_VERSION_MINOR 30
/**
* struct kbase_ioctl_version_check - Check version compatibility between
@@ -340,6 +356,8 @@ union kbase_ioctl_cs_queue_group_create_1_18 {
* @in.csi_handlers: Flags to signal that the application intends to use CSI
* exception handlers in some linear buffers to deal with
* the given exception types.
* @in.cs_fault_report_enable: Flag to indicate reporting of CS_FAULTs
* to userspace.
* @in.padding: Currently unused, must be zero
* @out: Output parameters
* @out.group_handle: Handle of a newly created queue group.
@@ -360,7 +378,8 @@ union kbase_ioctl_cs_queue_group_create {
/**
* @in.reserved: Reserved, currently unused, must be zero.
*/
__u16 reserved;
__u8 reserved;
__u8 cs_fault_report_enable;
/**
* @in.dvs_buf: buffer for deferred vertex shader
*/
@@ -480,7 +499,7 @@ union kbase_ioctl_cs_tiler_heap_init {
/**
* union kbase_ioctl_cs_tiler_heap_init_1_13 - Initialize chunked tiler memory heap,
* earlier version upto 1.13
* earlier version up to 1.13
* @in: Input parameters
* @in.chunk_size: Size of each chunk.
* @in.initial_chunks: Initial number of chunks that heap will be created with.
@@ -637,6 +656,22 @@ union kbase_ioctl_read_user_page {
#define KBASE_IOCTL_READ_USER_PAGE _IOWR(KBASE_IOCTL_TYPE, 60, union kbase_ioctl_read_user_page)
/**
* struct kbase_ioctl_queue_group_clear_faults - Re-enable CS FAULT reporting for the GPU queues
*
* @addr: CPU VA to an array of GPU VAs of the buffers backing the queues
* @nr_queues: Number of queues in the array
* @padding: Padding to round up to a multiple of 8 bytes, must be zero
*/
struct kbase_ioctl_queue_group_clear_faults {
__u64 addr;
__u32 nr_queues;
__u8 padding[4];
};
#define KBASE_IOCTL_QUEUE_GROUP_CLEAR_FAULTS \
_IOW(KBASE_IOCTL_TYPE, 61, struct kbase_ioctl_queue_group_clear_faults)
/***************
* test ioctls *
***************/

2
include/uapi/gpu/arm/bifrost/gpu/mali_kbase_gpu_id.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2015-2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2015-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software

23
include/uapi/gpu/arm/bifrost/jm/mali_base_jm_kernel.h
View File

@@ -30,15 +30,11 @@
* See base_mem_alloc_flags.
*/
/* Used as BASE_MEM_FIXED in other backends */
#define BASE_MEM_RESERVED_BIT_8 ((base_mem_alloc_flags)1 << 8)
/* Unused bit for JM, only used in CSF for BASE_MEM_FIXED */
#define BASE_MEM_UNUSED_BIT_8 ((base_mem_alloc_flags)1 << 8)
/**
* BASE_MEM_RESERVED_BIT_19 - Bit 19 is reserved.
*
* Do not remove, use the next unreserved bit for new flags
*/
#define BASE_MEM_RESERVED_BIT_19 ((base_mem_alloc_flags)1 << 19)
/* Unused bit for JM, only used in CSF for BASE_CSF_EVENT */
#define BASE_MEM_UNUSED_BIT_19 ((base_mem_alloc_flags)1 << 19)
/**
* BASE_MEM_TILER_ALIGN_TOP - Memory starting from the end of the initial commit is aligned
@@ -64,9 +60,14 @@
(BASEP_MEM_PERMANENT_KERNEL_MAPPING | BASEP_MEM_NO_USER_FREE | BASE_MEM_FLAG_MAP_FIXED | \
BASEP_MEM_PERFORM_JIT_TRIM)
/* A mask of all currently reserved flags
*/
#define BASE_MEM_FLAGS_RESERVED (BASE_MEM_RESERVED_BIT_8 | BASE_MEM_RESERVED_BIT_19)
/* A mask of all flags that should not be queried */
#define BASE_MEM_DONT_QUERY (BASE_MEM_COHERENT_SYSTEM_REQUIRED | BASE_MEM_IMPORT_SHARED)
/* A mask of all currently reserved flags */
#define BASE_MEM_FLAGS_RESERVED ((base_mem_alloc_flags)0)
/* A mask of all bits that are not used by a flag on JM */
#define BASE_MEM_FLAGS_UNUSED (BASE_MEM_UNUSED_BIT_8 | BASE_MEM_UNUSED_BIT_19)
/* Similar to BASE_MEM_TILER_ALIGN_TOP, memory starting from the end of the
* initial commit is aligned to 'extension' pages, where 'extension' must be a power

14
include/uapi/gpu/arm/bifrost/jm/mali_kbase_jm_ioctl.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2020-2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2020-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -149,15 +149,25 @@
* from the parent process.
* 11.40:
* - Remove KBASE_IOCTL_HWCNT_READER_SETUP and KBASE_HWCNT_READER_* ioctls.
* - Made the BASE_MEM_DONT_NEED memory flag queryable.
* 11.41:
* - Disallows changing the sharability on the GPU of imported dma-bufs to
* BASE_MEM_COHERENT_SYSTEM using KBASE_IOCTL_MEM_FLAGS_CHANGE.
* 11.42:
* - Implement full block state support for hardware counters.
* 11.43:
* - Made the BASE_MEM_IMPORT_SYNC_ON_MAP_UNMAP and BASE_MEM_KERNEL_SYNC memory
* flags queryable.
* 11.44:
* - Made the SAME_VA memory flag queryable.
* 11.45:
* - Re-allow child process to do supported file operations (like mmap, ioctl
* read, poll) on the file descriptor of mali device that was inherited
* from the parent process.
*/
#define BASE_UK_VERSION_MAJOR 11
#define BASE_UK_VERSION_MINOR 42
#define BASE_UK_VERSION_MINOR 45
/**
* struct kbase_ioctl_version_check - Check version compatibility between

25
include/uapi/gpu/arm/bifrost/mali_base_kernel.h
View File

@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
*
* (C) COPYRIGHT 2010-2023 ARM Limited. All rights reserved.
* (C) COPYRIGHT 2010-2024 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -89,10 +89,9 @@ typedef __u32 base_mem_alloc_flags;
/* A mask of all the flags that can be returned via the base_mem_get_flags()
* interface.
*/
#define BASE_MEM_FLAGS_QUERYABLE \
(BASE_MEM_FLAGS_INPUT_MASK & \
~(BASE_MEM_SAME_VA | BASE_MEM_COHERENT_SYSTEM_REQUIRED | BASE_MEM_IMPORT_SHARED | \
BASE_MEM_FLAGS_RESERVED | BASEP_MEM_FLAGS_KERNEL_ONLY))
#define BASE_MEM_FLAGS_QUERYABLE \
(BASE_MEM_FLAGS_INPUT_MASK & ~(BASE_MEM_DONT_QUERY | BASE_MEM_FLAGS_RESERVED | \
BASE_MEM_FLAGS_UNUSED | BASEP_MEM_FLAGS_KERNEL_ONLY))
/**
* enum base_mem_import_type - Memory types supported by @a base_mem_import
@@ -619,15 +618,15 @@ struct base_gpu_props {
#define BASE_TIMEINFO_TIMESTAMP_FLAG (1U << 1)
/* For GPU cycle counter */
#define BASE_TIMEINFO_CYCLE_COUNTER_FLAG (1U << 2)
/* Specify kernel GPU register timestamp */
#define BASE_TIMEINFO_KERNEL_SOURCE_FLAG (1U << 30)
/* Specify userspace cntvct_el0 timestamp source */
#define BASE_TIMEINFO_USER_SOURCE_FLAG (1U << 31)
#define BASE_TIMEREQUEST_ALLOWED_FLAGS \
(BASE_TIMEINFO_MONOTONIC_FLAG | BASE_TIMEINFO_TIMESTAMP_FLAG | \
BASE_TIMEINFO_CYCLE_COUNTER_FLAG | BASE_TIMEINFO_KERNEL_SOURCE_FLAG | \
BASE_TIMEINFO_USER_SOURCE_FLAG)
/* Specify TimeReques flags allowed if time source is cpu/gpu register */
#define BASE_TIMEREQUEST_CPU_GPU_SRC_ALLOWED_FLAGS \
(BASE_TIMEINFO_MONOTONIC_FLAG | BASE_TIMEINFO_TIMESTAMP_FLAG | \
BASE_TIMEINFO_CYCLE_COUNTER_FLAG)
/* Specify TimeReques flags allowed if time source is system(user) space */
#define BASE_TIMEREQUEST_SYSTEM_SRC_ALLOWED_FLAGS \
(BASE_TIMEINFO_MONOTONIC_FLAG | BASE_TIMEINFO_TIMESTAMP_FLAG)
/* Maximum number of source allocations allowed to create an alias allocation.
* This needs to be 4096 * 6 to allow cube map arrays with up to 4096 array