From 4d3dbab67b4cf6a04603cac873cff219bd313a6a Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Wed, 9 Apr 2025 16:47:57 +0800 Subject: [PATCH] clk: rockchip: rv1126b: Add ROCKCHIP_PLL_ALLOW_POWER_DOWN for aupll Signed-off-by: Finley Xiao Change-Id: If7d656534db6ec000ceabe4a6214ada01e1dd102 --- drivers/clk/rockchip/clk-rv1126b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rv1126b.c b/drivers/clk/rockchip/clk-rv1126b.c index 3c7907f82ec2..dd136c619c43 100644 --- a/drivers/clk/rockchip/clk-rv1126b.c +++ b/drivers/clk/rockchip/clk-rv1126b.c @@ -150,7 +150,8 @@ static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = { RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates), [aupll] = PLL(pll_rk3328, PLL_AUPLL, "aupll", mux_pll_p, 0, RV1126B_PLL_CON(0), - RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates), + RV1126B_MODE_CON, 0, 10, + ROCKCHIP_PLL_ALLOW_POWER_DOWN, rv1126b_pll_rates), [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0), RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates),