From 4da47ef026f4aac47ea8f92cc2fc22ed5c02f726 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Thu, 24 Dec 2020 17:35:11 +0800 Subject: [PATCH] PCI: rockchip: dw: Add compliance test mode support Change-Id: I93d2f84d6376221a296c747954acae2593c41d50 Signed-off-by: Shawn Lin --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 801180d6fd0e..a577686dd3e6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -1206,12 +1206,20 @@ static int rk_pcie_really_probe(void *p) /* Set PCIe mode */ rk_pcie_set_mode(rk_pcie); + /* Force into loopback master mode */ if (device_property_read_bool(dev, "rockchip,lpbk-master")) { val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); val |= PORT_LINK_LPBK_ENABLE; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); } + /* Force into compliance mode */ + if (device_property_read_bool(dev, "rockchip,compliance-mode")) { + val = dw_pcie_readl_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS); + val |= BIT(4); + dw_pcie_writel_dbi(pci, PCIE_CAP_LINK_CONTROL2_LINK_STATUS, val); + } + switch (rk_pcie->mode) { case RK_PCIE_RC_TYPE: ret = rk_add_pcie_port(rk_pcie);