From 4e89810905e1231250769558278c84faedf7a7da Mon Sep 17 00:00:00 2001
From: Shawn Lin <shawn.lin@rock-chips.com>
Date: Mon, 30 Sep 2024 17:29:57 +0800
Subject: [PATCH] perf/dwc_pcie: Fix lane event support for Rockchip

Lane event counter usage in Rockchip is slightly different with
T-Head. Fix it by checking vendor ID.

Fixes: 6cb6a00862fa ("perf/dwc_pcie: Add support for Rockchip vendor devices")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Iccc25bb7b352f73bae963d827f14b2f7405608b2
---
 drivers/perf/dwc_pcie_pmu.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c
index c0b8822e87bd..b4c6346270df 100644
--- a/drivers/perf/dwc_pcie_pmu.c
+++ b/drivers/perf/dwc_pcie_pmu.c
@@ -256,12 +256,31 @@ static const struct attribute_group *dwc_pcie_attr_groups[] = {
 	NULL
 };
 
+static void dwc_pcie_pmu_lane_event_enable_for_rk(struct pci_dev *pdev,
+						  u16 ras_des_offset,
+						  bool enable)
+{
+	if (enable) {
+		pci_write_config_dword(pdev,
+				ras_des_offset + DWC_PCIE_EVENT_CNT_CTL, 0x1c);
+		pci_write_config_dword(pdev,
+				ras_des_offset + DWC_PCIE_EVENT_CNT_CTL, 0x3);
+	} else {
+		pci_write_config_dword(pdev,
+				ras_des_offset + DWC_PCIE_EVENT_CNT_CTL, 0x14);
+	}
+}
+
 static void dwc_pcie_pmu_lane_event_enable(struct dwc_pcie_pmu *pcie_pmu,
 					   bool enable)
 {
 	struct pci_dev *pdev = pcie_pmu->pdev;
 	u16 ras_des_offset = pcie_pmu->ras_des_offset;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
+		return dwc_pcie_pmu_lane_event_enable_for_rk(pdev, ras_des_offset,
+							     enable);
+
 	if (enable)
 		pci_clear_and_set_config_dword(pdev,
 					ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
@@ -287,9 +306,13 @@ static u64 dwc_pcie_pmu_read_lane_event_counter(struct perf_event *event)
 {
 	struct dwc_pcie_pmu *pcie_pmu = to_dwc_pcie_pmu(event->pmu);
 	struct pci_dev *pdev = pcie_pmu->pdev;
+	int event_id = DWC_PCIE_EVENT_ID(event);
 	u16 ras_des_offset = pcie_pmu->ras_des_offset;
 	u32 val;
 
+	if (pdev->vendor == PCI_VENDOR_ID_ROCKCHIP)
+		pci_write_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_CTL,
+				       event_id << 16);
 	pci_read_config_dword(pdev, ras_des_offset + DWC_PCIE_EVENT_CNT_DATA, &val);
 
 	return val;