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arm64: cacheinfo: Avoid out-of-bounds write to cacheinfo array

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[ Upstream commit 875d742cf5327c93cba1f11e12b08d3cce7a88d2 ]

The loop that detects/populates cache information already has a bounds
check on the array size but does not account for cache levels with
separate data/instructions cache. Fix this by incrementing the index
for any populated leaf (instead of any populated level).

Fixes: 5d425c1865 ("arm64: kernel: add support for cpu cache information")

Signed-off-by: Radu Rendec <rrendec@redhat.com>
Link: https://lore.kernel.org/r/20250206174420.2178724-1-rrendec@redhat.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Radu Rendec
2025-02-06 12:44:20 -05:00
committed by Greg Kroah-Hartman
parent 4512482e48
commit 4ff25f0b18
1 changed files with 7 additions and 5 deletions
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12
arch/arm64/kernel/cacheinfo.c
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@@ -87,16 +87,18 @@ int populate_cache_leaves(unsigned int cpu)
unsigned int level, idx; unsigned int level, idx;
enum cache_type type; enum cache_type type;
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf = this_cpu_ci->info_list; struct cacheinfo *infos = this_cpu_ci->info_list;
for (idx = 0, level = 1; level <= this_cpu_ci->num_levels && for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
idx < this_cpu_ci->num_leaves; idx++, level++) { idx < this_cpu_ci->num_leaves; level++) {
type = get_cache_type(level); type = get_cache_type(level);
if (type == CACHE_TYPE_SEPARATE) { if (type == CACHE_TYPE_SEPARATE) {
ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level); if (idx + 1 >= this_cpu_ci->num_leaves)
ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level); break;
ci_leaf_init(&infos[idx++], CACHE_TYPE_DATA, level);
ci_leaf_init(&infos[idx++], CACHE_TYPE_INST, level);
} else { } else {
ci_leaf_init(this_leaf++, type, level); ci_leaf_init(&infos[idx++], type, level);
} }
} }
return 0; return 0;