diff --git a/arch/arm/configs/rv1106-recovery.config b/arch/arm/configs/rv1106-recovery.config
index a49e5b0c05de..73ccfebabee2 100644
--- a/arch/arm/configs/rv1106-recovery.config
+++ b/arch/arm/configs/rv1106-recovery.config
@@ -175,6 +175,7 @@ CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
 # CONFIG_CRYPTO_XTS is not set
 # CONFIG_CRYPTO_XXHASH is not set
 # CONFIG_CRYPTO_ZSTD is not set
+CONFIG_DECOMPRESS_GZIP=y
 # CONFIG_EEPROM_93XX46 is not set
 # CONFIG_EEPROM_AT25 is not set
 # CONFIG_EXT4_DEBUG is not set
@@ -290,7 +291,7 @@ CONFIG_MTD_UBI_WL_THRESHOLD=4096
 CONFIG_PWRSEQ_EMMC=y
 CONFIG_PWRSEQ_SIMPLE=y
 # CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_GZIP is not set
+CONFIG_RD_GZIP=y
 # CONFIG_RD_LZ4 is not set
 # CONFIG_RD_LZMA is not set
 # CONFIG_RD_LZO is not set
diff --git a/drivers/clk/rockchip/clk-rv1106.c b/drivers/clk/rockchip/clk-rv1106.c
index 0833bf2adb8b..f61cbbf2e81d 100644
--- a/drivers/clk/rockchip/clk-rv1106.c
+++ b/drivers/clk/rockchip/clk-rv1106.c
@@ -1135,7 +1135,7 @@ static void rockchip_rv1106_pvtpll_init(struct rockchip_clk_provider *ctx)
 	writel_relaxed(0xffff0004, ctx->reg_base + CRU_PVTPLL1_CON2_H);
 	writel_relaxed(0x00030003, ctx->reg_base + CRU_PVTPLL1_CON0_L);
 
-	schedule_delayed_work(&pvtpll_calibrate_work, msecs_to_jiffies(3000));
+	queue_delayed_work(system_freezable_wq, &pvtpll_calibrate_work, msecs_to_jiffies(300));
 }
 
 static int rv1106_clk_panic(struct notifier_block *this,
diff --git a/drivers/video/rockchip/mpp/mpp_rkvenc2.c b/drivers/video/rockchip/mpp/mpp_rkvenc2.c
index c132b53e4752..4f10e080da2e 100644
--- a/drivers/video/rockchip/mpp/mpp_rkvenc2.c
+++ b/drivers/video/rockchip/mpp/mpp_rkvenc2.c
@@ -1272,12 +1272,25 @@ static int rkvenc_run(struct mpp_dev *mpp, struct mpp_task *mpp_task)
 }
 
 static void rkvenc2_read_slice_len(struct mpp_dev *mpp, struct rkvenc_task *task,
-				   u32 last)
+				   u32 *irq_status)
 {
+	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
+	struct rkvenc_hw_info *hw = enc->hw_info;
 	u32 sli_num = mpp_read_relaxed(mpp, RKVENC2_REG_SLICE_NUM_BASE);
+	u32 new_irq_status = mpp_read(mpp, hw->int_sta_base);
 	union rkvenc2_slice_len_info slice_info;
 	u32 task_id = task->mpp_task.task_id;
 	u32 i;
+	u32 last = 0;
+
+	/* Need update irq status and slice number when enc done ready with new status*/
+	if ((new_irq_status != *irq_status) && (new_irq_status & INT_STA_ENC_DONE_STA)) {
+		*irq_status |= new_irq_status;
+		sli_num = mpp_read_relaxed(mpp, RKVENC2_REG_SLICE_NUM_BASE);
+		mpp_write(mpp, hw->int_clr_base, new_irq_status);
+	}
+
+	last = *irq_status & INT_STA_ENC_DONE_STA;
 
 	mpp_dbg_slice("task %d wr %3d len start %s\n", task_id,
 		      sli_num, last ? "last" : "");
@@ -1346,7 +1359,7 @@ static int rkvenc_irq(struct mpp_dev *mpp)
 	if (task && task->task_split &&
 	    (irq_status & (INT_STA_SLC_DONE_STA | INT_STA_ENC_DONE_STA))) {
 		mpp_time_part_diff(mpp_task);
-		rkvenc2_read_slice_len(mpp, task, irq_status & INT_STA_ENC_DONE_STA);
+		rkvenc2_read_slice_len(mpp, task, &irq_status);
 		wake_up(&mpp_task->wait);
 	}