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clk: rockchip: rv1126b: export secure clks

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Change-Id: I79fddf648f49b3c46103c7717661a479ddf7bc49
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This commit is contained in:
Elaine Zhang
2025-03-25 10:14:36 +08:00
committed by Tao Huang
parent 2fe8584c3f
commit 50b60d3d4c
2 changed files with 28 additions and 6 deletions
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12
drivers/clk/rockchip/clk-rv1126b.c
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@@ -421,7 +421,7 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
COMPOSITE_NODIV(TCLK_WDT_NS_SRC, "tclk_wdt_ns_src", mux_100m_24m_p, 0,
RV1126B_CLKSEL_CON(46), 12, 1, MFLAGS,
RV1126B_CLKGATE_CON(8), 0, GFLAGS),
COMPOSITE_NODIV(TCLK_WDT_S, "tclk_wdt_s", mux_100m_24m_p, 0,
COMPOSITE_NODIV(TCLK_WDT_S_SRC, "tclk_wdt_s_src", mux_100m_24m_p, 0,
RV1126B_CLKSEL_CON(46), 13, 1, MFLAGS,
RV1126B_CLKGATE_CON(8), 1, GFLAGS),
COMPOSITE_NODIV(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", mux_100m_24m_p, 0,
@@ -459,10 +459,10 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_24m_p, 0,
RV1126B_CLKSEL_CON(50), 11, 1, MFLAGS,
RV1126B_CLKGATE_CON(9), 3, GFLAGS),
COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, 0,
COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, CLK_IS_CRITICAL,
RV1126B_CLKSEL_CON(50), 12, 1, MFLAGS,
RV1126B_CLKGATE_CON(9), 4, GFLAGS),
COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, 0,
COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, CLK_IS_CRITICAL,
RV1126B_CLKSEL_CON(50), 13, 1, MFLAGS,
RV1126B_CLKGATE_CON(9), 5, GFLAGS),
COMPOSITE_NODIV(ACLK_VCP_ROOT, "aclk_vcp_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL,
@@ -865,6 +865,10 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0,
RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS,
RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS),
GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_bus_root", 0,
RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS),
GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0,
RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS),
GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0,
@@ -948,7 +952,7 @@ static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
GATE(MCLK_AUDIO_ADC_BUS, "mclk_audio_adc_bus", "mclk_sai2", 0,
RV1126B_BUSCLKGATE_CON(5), 14, GFLAGS),
FACTOR(MCLK_AUDIO_ADC_DIV4_BUS, "mclk_audio_adc_div4_bus", "mclk_audio_adc_bus", 0, 1, 4),
GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", 0,
GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", CLK_IS_CRITICAL,
RV1126B_BUSCLKGATE_CON(6), 0, GFLAGS),
GATE(HCLK_NS_RKCE, "hclk_ns_rkce", "hclk_bus_root", 0,
RV1126B_BUSCLKGATE_CON(6), 1, GFLAGS),

22
include/dt-bindings/clock/rockchip,rv1126b-cru.h
View File

@@ -94,7 +94,7 @@
#define CLK_GMAC_125M 84
#define CLK_TIMER_ROOT 85
#define TCLK_WDT_NS_SRC 86
#define TCLK_WDT_S 87
#define TCLK_WDT_S_SRC 87
#define TCLK_WDT_HPMCU 88
#define CLK_CAN0 89
#define CLK_CAN1 90
@@ -369,8 +369,26 @@
#define ACLK_VPSL 359
#define CLK_CORE_VPSL 360
#define CLK_MACPHY 361
#define HCLK_RKRNG_NS 362
#define HCLK_RKRNG_S_NS 362
#define CLK_NR_CLKS (CLK_MACPHY + 1)
/* secure clks */
#define CLK_USER_OTPC_S 400
#define CLK_SBPI_OTPC_S 401
#define PCLK_OTPC_S 402
#define PCLK_KEY_READER_S 403
#define HCLK_KL_RKCE_S 404
#define HCLK_RKCE_S 405
#define PCLK_WDT_S 406
#define TCLK_WDT_S 407
#define CLK_STIMER0 408
#define CLK_STIMER1 409
#define PLK_STIMER 410
#define HCLK_RKRNG_S 411
#define CLK_PKA_RKCE_S 412
#define ACLK_RKCE_S 413
#define CLK_NR_CLKS (ACLK_RKCE_S + 1)
// ======================= TOPCRU module definition bank=0 ========================
// TOPCRU_SOFTRST_CON15(Offset:0xA3C)