From 50e757f7cbfa06b9a31fe458be1da48fb6c4e572 Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Thu, 14 Apr 2022 03:26:29 +0000 Subject: [PATCH] phy/rockchip: samsung-hdptx: Disable TX jitter EQ for power reduction Signed-off-by: Wyon Bi Change-Id: Ia5a0901182deb47b1a8599922efbcf60101ce15c --- .../phy/rockchip/phy-rockchip-samsung-hdptx.c | 22 ------------------- 1 file changed, 22 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 10d8ff68bc5e..2aee0c9b6684 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -491,31 +491,15 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, { const struct tx_drv_ctrl *ctrl; - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), - LN_ANA_TX_JEQ_EN, - FIELD_PREP(LN_ANA_TX_JEQ_EN, 0x1)); - switch (dp->link_rate) { case 1620: ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c28), - LN_TX_JEQ_EVEN_CTRL_RBR, - FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR, 0x7)); - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c30), - LN_TX_JEQ_ODD_CTRL_RBR, - FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR, 0x7)); regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_RBR, FIELD_PREP(LN_TX_SER_40BIT_EN_RBR, 0x1)); break; case 2700: ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), - LN_TX_JEQ_EVEN_CTRL_HBR, - FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR, 0x7)); - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34), - LN_TX_JEQ_ODD_CTRL_HBR, - FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR, 0x7)); regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_HBR, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR, 0x1)); @@ -523,12 +507,6 @@ static void rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, case 5400: default: ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c2c), - LN_TX_JEQ_EVEN_CTRL_HBR2, - FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2, 0x7)); - regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c34), - LN_TX_JEQ_ODD_CTRL_HBR2, - FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2, 0x7)); regmap_update_bits(hdptx->regmap, LANE_REG(lane, 0x0c44), LN_TX_SER_40BIT_EN_HBR2, FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2, 0x1));