From 512465e0c04762d5ffccff0b3f8ef18d8a56acac Mon Sep 17 00:00:00 2001
From: Liang Chen <cl@rock-chips.com>
Date: Thu, 16 May 2024 10:51:56 +0800
Subject: [PATCH] arm64: dts: rockchip: add core dtsi for RK3566RPO Soc

Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I81430bfcce410ddf9205e1b37482b7b869e4f556
---
 arch/arm64/boot/dts/rockchip/rk3566pro.dtsi | 45 +++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3566pro.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3566pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3566pro.dtsi
new file mode 100644
index 000000000000..f51ff6197678
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566pro.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2025 Rockchip Electronics Co., Ltd.
+ */
+
+#include "rk356x.dtsi"
+
+/ {
+	compatible = "rockchip,rk3566pro", "rockchip,rk3566";
+};
+
+&pipegrf {
+	compatible = "rockchip,rk3566-pipe-grf", "syscon";
+};
+
+&power {
+	power-domain@RK3568_PD_PIPE {
+		reg = <RK3568_PD_PIPE>;
+		clocks = <&cru PCLK_PIPE>;
+		pm_qos = <&qos_pcie2x1>,
+			 <&qos_sata1>,
+			 <&qos_sata2>,
+			 <&qos_usb3_0>,
+			 <&qos_usb3_1>;
+		#power-domain-cells = <0>;
+	};
+};
+
+&rkisp {
+	rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>;
+};
+
+&usbdrd_dwc3 {
+	phys = <&u2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+	snps,dis_u2_susphy_quirk;
+	snps,usb2-lpm-disable;
+};
+
+/delete-node/ &route_edp;
+/delete-node/ &vp0_out_edp;
+/delete-node/ &vp1_out_edp;
+/delete-node/ &edp;