From 5134a48cbe80cc64d65dbc95023c6277534ad784 Mon Sep 17 00:00:00 2001 From: ckkim Date: Thu, 30 Oct 2014 18:29:26 +0900 Subject: [PATCH] mmc/sdhc: Fix clk_div for maximum clock Change-Id: I5dabc4071c2f1d2d4f4ea550097b990757c74e99 Signed-off-by: Kevin Kim (cherry picked from commit 18dc68ff78151320c4a6133f5731448d2ac4f500) Signed-off-by: Dongjin Kim --- drivers/amlogic/mmc/aml_sdhc_m8.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/amlogic/mmc/aml_sdhc_m8.c b/drivers/amlogic/mmc/aml_sdhc_m8.c index 58781c18a8c5..d4f0d5fd1c9f 100755 --- a/drivers/amlogic/mmc/aml_sdhc_m8.c +++ b/drivers/amlogic/mmc/aml_sdhc_m8.c @@ -1988,8 +1988,10 @@ static void aml_sdhc_set_clk_rate(struct mmc_host *mmc, unsigned int clk_ios) /*0: dont set it, 1:div2, 2:div3, 3:div4...*/ clk_div = clk_rate / clk_ios - !(clk_rate%clk_ios); +#if !defined(CONFIG_MACH_MESON8B_ODROIDC) if (!(clk_div & 0x01)) // if even number, turn it to an odd one clk_div++; +#endif aml_sdhc_clk_switch(pdata, clk_div, clk_src_sel); pdata->clkc = readl(host->base+SDHC_CLKC);