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rk2928:sdk: fix pll_mode POWER ON/DN ERROR

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This commit is contained in:
chenxing
2012-08-27 14:08:51 +08:00
parent d58b44f6fd
commit 515638e7d9
2 changed files with 5 additions and 4 deletions
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5
arch/arm/mach-rk2928/clock_data.c
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@@ -545,6 +545,7 @@ static void pll_wait_lock(int pll_idx)
while(1);
}
}
static int pll_clk_mode(struct clk *clk, int on)
{
u8 pll_id = clk->pll->id;
@@ -554,13 +555,13 @@ static int pll_clk_mode(struct clk *clk, int on)
CLKDATA_DBG("pll_mode %s(%d)\n", clk->name, on);
//FIXME
if (on) {
cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_ON, PLL_LOCK_SHIFT), PLL_CONS(pll_id, 1));
cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_ON, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0));
rk_clock_udelay(dly);
pll_wait_lock(pll_id);
cru_writel(PLL_MODE_NORM(pll_id), CRU_MODE_CON);
} else {
cru_writel(PLL_MODE_SLOW(pll_id), CRU_MODE_CON);
cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_DN, PLL_LOCK_SHIFT), PLL_CONS(pll_id, 1));
cru_writel(CRU_W_MSK_SETBIT(PLL_PWR_DN, PLL_BYPASS_SHIFT), PLL_CONS(pll_id, 0));
}
return 0;
}

4
arch/arm/mach-rk2928/include/mach/cru.h
View File

@@ -33,8 +33,8 @@ enum rk_plls_id {
#define CRU_GLB_CNT_TH (0x140)
/*PLL_CON 0,1,2*/
#define PLL_PWR_ON (1)
#define PLL_PWR_DN (0)
#define PLL_PWR_ON (0)
#define PLL_PWR_DN (1)
#define PLL_BYPASS (1 << 15)
#define PLL_NO_BYPASS (0 << 15)
//con0