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vlock: screen flash after PAL NTSC swich [1/1]

Browse Source 
PD#SWPL-4246

Problem:
the screen always flash after switch PAL to NTSC in AVin

Solution:
do not change pll M value, M value will case v by one fail

Verify:
verified on tl1 android p

Change-Id: Ib5ea8dfef1c40af5535e69fdc9241a7f77b4a7dd
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
This commit is contained in:
Yong Qin
2019-01-01 10:28:08 +08:00
committed by Jianxin Pan
parent 032a712f67
commit 51822f95f4
4 changed files with 278 additions and 71 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/amlogic/media/enhancement/amvecm/amvecm.c
View File

@@ -736,6 +736,14 @@ static ssize_t amvecm_vlock_store(struct class *cla,
vlock_log_stop();
} else if (!strncmp(parm[0], "log_print", 9)) {
vlock_log_print();
} else if (!strncmp(parm[0], "phase", 5)) {
if (kstrtol(parm[1], 10, &val) < 0)
return -EINVAL;
vlock_set_phase(val);
} else if (!strncmp(parm[0], "phaseen", 7)) {
if (kstrtol(parm[1], 10, &val) < 0)
return -EINVAL;
vlock_set_phase_en(val);
} else {
pr_info("unsupport cmd!!\n");
}
@@ -6023,7 +6031,7 @@ static const struct vecm_match_data_s vecm_dt_tl1 = {
.vlk_support = true,
.vlk_new_fsm = 1,
.vlk_hwver = vlock_hw_ver2,
.vlk_phlock_en = true,
.vlk_phlock_en = false,
};
static const struct of_device_id aml_vecm_dt_match[] = {

6
drivers/amlogic/media/enhancement/amvecm/amvecm_vlock_regmap.h
View File

@@ -54,15 +54,15 @@ static struct vlock_regs_s vlock_pll_setting[VLOCK_DEFAULT_REG_SIZE] = {
{0x3001, 0x04053c32 },
{0x3002, 0x06000000 },
{0x3003, 0x20780780 },
{0x3004, 0x00000000 },
{0x3004, 0x00680680 },
{0x3005, 0x00080000 },
{0x3006, 0x00070000 },
{0x3007, 0x00000000 },
{0x3008, 0x00000000 },
{0x3009, 0x00100000 },
{0x300a, 0x00600000 },
{0x300a, 0x00008000 },/*0x00600000*/
{0x300b, 0x00100000 },
{0x300c, 0x00000000 },
{0x300c, 0x00600000 },
{0x300d, 0x00004000 },
{0x3010, 0x20001000 },
{0x3016, 0x0003de00 },

309
drivers/amlogic/media/enhancement/amvecm/vlock.c
View File

@@ -198,33 +198,41 @@ static unsigned int vlock_check_input_hz(struct vframe_s *vf)
return ret_hz;
}
static unsigned int vlock_check_output_hz(unsigned int sync_duration_num)
static unsigned int vlock_check_output_hz(unsigned int sync_duration_num,
unsigned int sync_duration_den)
{
unsigned int ret_hz = 0;
unsigned int tempHz;
switch (sync_duration_num) {
case 24:
tempHz = (sync_duration_num*100)/sync_duration_den;
switch (tempHz) {
case 2400:
ret_hz = 24;
break;
case 30:
case 3000:
ret_hz = 30;
break;
case 50:
case 5000:
ret_hz = 50;
break;
case 60:
case 6000:
ret_hz = 60;
break;
case 100:
case 10000:
ret_hz = 100;
break;
case 120:
case 12000:
ret_hz = 120;
break;
default:
ret_hz = 0;
break;
}
if ((ret_hz == 0) && (vlock_debug & VLOCK_DEBUG_INFO))
pr_info("sync_duration_num:%d\n", sync_duration_num);
return ret_hz;
}
/*vlock is support eq_after gxbb,but which is useful only for tv chip
@@ -255,30 +263,19 @@ static void vlock_enable(bool enable)
else
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL5,
enable, 3, 1);
} else if (is_meson_tl1_cpu()) {
} else if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
/*reset*/
if (vlock_mode & VLOCK_MODE_MANUAL_PLL) {
#if 0
if (enable == 1) {
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("tl1 vlock enable\n");
amvecm_hiu_reg_write_bits(hhi_pll_reg_vlock_ctl,
1, 0, 1);
} else {
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("tl1 vlock disable\n");
amvecm_hiu_reg_write_bits(hhi_pll_reg_vlock_ctl,
0, 0, 1);
}
#endif
} else {
if (!(vlock_mode & VLOCK_MODE_MANUAL_PLL)) {
/*reset*/
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 5, 1);
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);
if (!enable)
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0, 1, 2);
}
if (!enable) {
/*amvecm_hiu_reg_write_bits(*/
/* HHI_HDMI_PLL_VLOCK_CNTL, 0, 0, 3);*/
/*WRITE_VPP_REG(VPU_VLOCK_CTRL, 0);*/
}
}
@@ -415,6 +412,12 @@ static void vlock_setting(struct vframe_s *vf,
amvecm_hiu_reg_read(hhi_pll_reg_m, &hiu_reg_value);
amvecm_hiu_reg_read(hhi_pll_reg_frac,
&hiu_reg_value_2);
if (vlock_debug & VLOCK_DEBUG_INFO) {
pr_info("hhi_pll_reg_m:0x%x\n", hiu_reg_value);
pr_info("hhi_pll_reg_frac:0x%x\n", hiu_reg_value_2);
}
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
hiu_m_val = hiu_reg_value & 0xff;
/*discard low 5 bits*/
@@ -457,6 +460,19 @@ static void vlock_setting(struct vframe_s *vf,
/* enable to adjust pll */
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 29, 1);
}
/*initial phase lock setting*/
if (vlock.dtdata->vlk_phlock_en) {
/*WRITE_VPP_REG(VPU_VLOCK_OUTPUT0_CAPT_LMT, 0x06000000);*/
WRITE_VPP_REG(VPU_VLOCK_OUTPUT0_CAPT_LMT, 0x06000000);
WRITE_VPP_REG(VPU_VLOCK_OUTPUT0_PLL_LMT, 0x06000000);
WRITE_VPP_REG(VPU_VLOCK_OUTPUT1_CAPT_LMT, 0x06000000);
WRITE_VPP_REG(VPU_VLOCK_OUTPUT1_PLL_LMT, 0x06000000);
/*enable pll mode and enc mode phase lock*/
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 3, 0, 2);
}
/* vlock module output goes to which module */
switch (READ_VPP_REG_BITS(VPU_VIU_VENC_MUX_CTRL, 0, 2)) {
case 0:/* ENCL */
@@ -564,7 +580,8 @@ static void vlock_disable_step1(void)
if ((vlock_mode & (VLOCK_MODE_MANUAL_PLL |
VLOCK_MODE_AUTO_PLL |
VLOCK_MODE_MANUAL_SOFT_ENC))) {
if (cpu_after_eq(MESON_CPU_MAJOR_ID_TL1)) {
if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
#if 0
amvecm_hiu_reg_read(hhi_pll_reg_frac,
&tmp_value);
m_reg_value = (tmp_value >> 5) & 0xfff;
@@ -573,6 +590,7 @@ static void vlock_disable_step1(void)
(pre_hiu_reg_frac & 0xfff);
amvecm_hiu_reg_write(hhi_pll_reg_frac,
tmp_value);
pr_info("restore f value=0x%x\n", tmp_value);
}
amvecm_hiu_reg_read(hhi_pll_reg_m, &tmp_value);
m_reg_value = tmp_value & 0xff;
@@ -581,7 +599,25 @@ static void vlock_disable_step1(void)
tmp_value = (tmp_value & 0xffffff00) |
(pre_hiu_reg_m & 0xff);
amvecm_hiu_reg_write(hhi_pll_reg_m, tmp_value);
pr_info("restore m value=0x%x\n", tmp_value);
}
#endif
#if 1
/*restore the orginal pll setting*/
amvecm_hiu_reg_read(hhi_pll_reg_m, &tmp_value);
m_reg_value = tmp_value & 0xff;
if (m_reg_value != (vlock.val_m & 0xff))
amvecm_hiu_reg_write(hhi_pll_reg_m,
vlock.val_m);
amvecm_hiu_reg_read(hhi_pll_reg_frac, &tmp_value);
m_reg_value = tmp_value & 0x1ffff;
if (m_reg_value != (vlock.val_frac & 0xfff))
amvecm_hiu_reg_write(hhi_pll_reg_frac,
vlock.val_frac);
pr_info("restore orignal m,f value\n");
#endif
} else {
amvecm_hiu_reg_read(hhi_pll_reg_frac, &tmp_value);
m_reg_value = tmp_value & 0xfff;
@@ -635,14 +671,22 @@ static void vlock_disable_step1(void)
pr_info(">>>[%s]\n", __func__);
}
static void vlock_disable_step2(void)
static bool vlock_disable_step2(void)
{
unsigned int temp_val;
bool ret = false;
/* need delay to disable follow regs(vlsi suggest!!!) */
if (vlock_dis_cnt > 0)
vlock_dis_cnt--;
if (vlock_dis_cnt == 0) {
else if (vlock_dis_cnt == 0) {
if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x4, 0, 3);
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x0, 0, 3);
}
/* disable to adjust pll */
WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 29, 1);
/* CFG_VID_LOCK_ADJ_EN disable */
@@ -659,10 +703,13 @@ static void vlock_disable_step2(void)
amvecm_hiu_reg_write_bits(HHI_HDMI_PLL_CNTL6,
0, 21, 2);
}
ret = true;
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info(">>>[%s]\n", __func__);
}
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info(">>>[%s]\n", __func__);
return ret;
}
static void vlock_enable_step1(struct vframe_s *vf, struct vinfo_s *vinfo,
unsigned int input_hz, unsigned int output_hz)
@@ -1075,8 +1122,18 @@ static void vlock_enable_step3_pll(void)
else
vlock_pll_stable_cnt = 0;
} else {
tmp_value = (tmp_value & 0xfff80000) |
((m_reg_value & 0xfff) << 5);
abs_val = abs((tmp_value & 0x1ffff) -
((m_reg_value & 0xfff) << 5));
if (abs_val > (50 << 5))
tmp_value = ((tmp_value & 0xfffe0000) |
(((tmp_value & 0x1ffff) +
((m_reg_value & 0xfff) << 5)) >> 1));
else
tmp_value = (tmp_value & 0xfffe0000) |
((m_reg_value & 0xfff) << 5);
/*16:0*/
amvecm_hiu_reg_write(hhi_pll_reg_frac, tmp_value);
}
@@ -1101,9 +1158,17 @@ static void vlock_enable_step3_pll(void)
vlock_pll_val_last |= (m_reg_value & 0xffff0000);
}
} else {
tmp_value = (tmp_value & 0xffffff00) |
((m_reg_value >> 16) & 0xff);
amvecm_hiu_reg_write(hhi_pll_reg_m, tmp_value);
if ((tmp_value & 0xff) !=
((m_reg_value >> 16) & 0xff)) {
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("vlock err: m chg: org=0x%x, new=0x%x\n",
(tmp_value & 0xff), (m_reg_value >> 16) & 0xff);
#if 0
tmp_value = (tmp_value & 0xffffff00) |
((m_reg_value >> 16) & 0xff);
amvecm_hiu_reg_write(hhi_pll_reg_m, tmp_value);
#endif
}
}
/*check stable by diff m*/
@@ -1133,7 +1198,8 @@ void amve_vlock_process(struct vframe_s *vf)
}
vinfo = get_current_vinfo();
input_hz = vlock_check_input_hz(vf);
output_hz = vlock_check_output_hz(vinfo->sync_duration_num);
output_hz = vlock_check_output_hz(vinfo->sync_duration_num,
vinfo->sync_duration_den);
vlock_dis_cnt_no_vf = 0;
if (vecm_latch_flag & FLAG_VLOCK_EN) {
vlock_enable_step1(vf, vinfo, input_hz, output_hz);
@@ -1227,11 +1293,18 @@ void amve_vlock_process(struct vframe_s *vf)
//WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);
vlock_state = VLOCK_STATE_ENABLE_STEP2_DONE;
/*tl1 auto pll,swich clk need after several frames*/
if (is_meson_tl1_cpu() &&
(vlock_mode & VLOCK_MODE_AUTO_PLL))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x3, 1, 2);
/*
* tl1 auto pll,swich clk need after
*several frames
*/
if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
if (IS_AUTO_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x7, 0, 3);
else if (IS_MANUAL_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x6, 0, 3);
}
if (vlock_debug & VLOCK_DEBUG_INFO)
pr_info("amve_vlock_process-2\n");
@@ -1326,6 +1399,8 @@ void vlock_set_en(bool en)
void vlock_status_init(void)
{
unsigned int val;
/*config vlock mode*/
/*todo:txlx & g9tv support auto pll,*/
/*but support not good,need vlsi support optimize*/
@@ -1350,11 +1425,22 @@ void vlock_status_init(void)
hhi_pll_reg_frac = HHI_HDMI_PLL_CNTL2;
}
/*back up orignal pll value*/
amvecm_hiu_reg_read(hhi_pll_reg_m, &val);
vlock.val_m = val;
pr_info("HIU pll m[0x%x]=0x%x\n",
hhi_pll_reg_m, val);
amvecm_hiu_reg_read(hhi_pll_reg_frac, &val);
vlock.val_frac = val;
pr_info("HIU pll f[0x%x]=0x%x\n",
hhi_pll_reg_frac, val);
vlock.fsm_sts = VLOCK_STATE_NULL;
vlock.fsm_prests = VLOCK_STATE_NULL;
vlock.vf_sts = false;
vlock.vmd_chg = false;
vlock.md_support = false;
vlock.phlock_percent = 40;
vlock_clear_frame_counter();
pr_info("%s vlock_en:%d\n", __func__, vlock_en);
}
@@ -1369,6 +1455,43 @@ void vlock_dt_match_init(struct vecm_match_data_s *pdata)
pr_info("vlock dt phlock_en: %d\n", vlock.dtdata->vlk_phlock_en);
}
void vlock_set_phase(u32 percent)
{
u32 vs_i_val = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
/*u32 vs_o_val = READ_VPP_REG(VPU_VLOCK_RO_VS_O_DIST);*/
u32 data = 0;
if (!vlock.dtdata->vlk_phlock_en)
return;
if (percent > 100) {
pr_info("percent val err:%d\n", percent);
return;
}
vlock.phlock_percent = percent;
data = (vs_i_val * (100 + vlock.phlock_percent))/200;
WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, data);
pr_info("LOOP1_PHSDIF_TGT:0x%x\n", data);
/*reset*/
data = READ_VPP_REG(VPU_VLOCK_CTRL);
data |= 1 << 2;
data |= 1 << 5;
WRITE_VPP_REG(VPU_VLOCK_CTRL, data);
data &= ~(1 << 2);
data &= ~(1 << 5);
WRITE_VPP_REG(VPU_VLOCK_CTRL, data);
}
void vlock_set_phase_en(u32 en)
{
if (en)
vlock.dtdata->vlk_phlock_en = true;
else
vlock.dtdata->vlk_phlock_en = false;
}
#if 1
u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
@@ -1382,9 +1505,13 @@ u32 vlock_fsm_check_support(struct stvlock_sig_sts *pvlock,
!= VIDTYPE_PROGRESSIVE) &&
is_meson_txlx_package_962E())) {
if (vlock_debug & VLOCK_DEBUG_INFO)
if (vlock_debug & VLOCK_DEBUG_INFO) {
pr_info("[%s] for no support case!!!\n",
__func__);
pr_info("input_hz:%d, output_hz:%d\n",
pvlock->input_hz, pvlock->output_hz);
pr_info("type_original:0x%x\n", vf->type_original);
}
ret = false;
}
@@ -1409,11 +1536,13 @@ u32 vlock_fsm_input_check(struct stvlock_sig_sts *vlock, struct vframe_s *vf)
else
vframe_sts = true;
vlock_vmode_check();
if (vf != NULL) {
vinfo = get_current_vinfo();
vlock->input_hz = vlock_check_input_hz(vf);
vlock->output_hz = vlock_check_output_hz(
vinfo->sync_duration_num);
vinfo->sync_duration_num, vinfo->sync_duration_den);
}
/*check vf exist status*/
@@ -1449,6 +1578,16 @@ u32 vlock_fsm_to_en_func(struct stvlock_sig_sts *pvlock,
vlock_vmode_changed ||
(pvlock->fsm_sts ==
VLOCK_STATE_ENABLE_FORCE_RESET)) {
/*back up orignal pll value*/
amvecm_hiu_reg_read(hhi_pll_reg_m, &vlock.val_m);
amvecm_hiu_reg_read(hhi_pll_reg_frac, &vlock.val_frac);
if (vlock_debug & VLOCK_DEBUG_INFO) {
pr_info("HIU pll m[0x%x]=0x%x\n",
hhi_pll_reg_m, vlock.val_m);
pr_info("HIU pll f[0x%x]=0x%x\n",
hhi_pll_reg_frac, vlock.val_frac);
}
vinfo = get_current_vinfo();
vlock_enable_step1(vf, vinfo,
pvlock->input_hz, pvlock->output_hz);
@@ -1507,10 +1646,14 @@ u32 vlock_fsm_en_step1_func(struct stvlock_sig_sts *pvlock,
* tl1 auto pll,swich clk need after
*several frames
*/
if (is_meson_tl1_cpu() &&
IS_AUTO_PLL_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x3, 1, 2);
if (vlock.dtdata->vlk_hwver >= vlock_hw_ver2) {
if (IS_AUTO_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x7, 0, 3);
else if (IS_MANUAL_MODE(vlock_mode))
amvecm_hiu_reg_write_bits(
HHI_HDMI_PLL_VLOCK_CNTL, 0x6, 0, 3);
}
ret = 1;
if (vlock_debug & VLOCK_DEBUG_INFO)
@@ -1520,6 +1663,28 @@ u32 vlock_fsm_en_step1_func(struct stvlock_sig_sts *pvlock,
return ret;
}
void vlock_phaselock_check(struct stvlock_sig_sts *pvlock,
struct vframe_s *vf)
{
/*vs_i*/
u32 ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
u32 val;
if (vlock.dtdata->vlk_phlock_en) {
ia = READ_VPP_REG(VPU_VLOCK_RO_VS_I_DIST);
val = (ia * (100 + vlock.phlock_percent))/200;
WRITE_VPP_REG(VPU_VLOCK_LOOP1_PHSDIF_TGT, val);
/*reset*/
/*WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 2, 1);*/
/*WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 1, 5, 1);*/
/*WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 2, 1);*/
/*WRITE_VPP_REG_BITS(VPU_VLOCK_CTRL, 0, 5, 1);*/
}
}
u32 vlock_fsm_en_step2_func(struct stvlock_sig_sts *pvlock,
struct vframe_s *vf)
{
@@ -1534,10 +1699,10 @@ u32 vlock_fsm_en_step2_func(struct stvlock_sig_sts *pvlock,
vlock_enable_step3_pll();
else if (IS_MANUAL_SOFTENC_MODE(vlock_mode))
vlock_enable_step3_soft_enc();
/*check stable*/
/*....*/
}
/*check phase*/
vlock_phaselock_check(pvlock, vf);
return ret;
}
@@ -1547,12 +1712,11 @@ void vlock_fsm_monitor(struct vframe_s *vf)
u32 changed;
changed = vlock_fsm_input_check(&vlock, vf);
vlock_vmode_check();
switch (vlock.fsm_sts) {
case VLOCK_STATE_NULL:
if (vlock.vf_sts) {
/*have frame in*/
if (vlock.frame_cnt_in++ == 3) {
if (vlock.frame_cnt_in++ >= 20) {
/*vframe input valid*/
if (vlock.md_support) {
if (vlock_fsm_to_en_func(&vlock, vf)) {
@@ -1625,20 +1789,21 @@ void vlock_fsm_monitor(struct vframe_s *vf)
/*go to disable state*/
vlock_clear_frame_counter();
vlock.fsm_sts = VLOCK_STATE_DISABLE_STEP1_DONE;
} else {
vlock_fsm_en_step2_func(&vlock, vf);
}
}
break;
case VLOCK_STATE_DISABLE_STEP1_DONE:
vlock_disable_step1();
vlock.fsm_sts = VLOCK_STATE_DISABLE_STEP2_DONE;
if (vlock_disable_step2())
vlock.fsm_sts = VLOCK_STATE_NULL;
else
vlock.fsm_sts = VLOCK_STATE_DISABLE_STEP2_DONE;
break;
case VLOCK_STATE_DISABLE_STEP2_DONE:
vlock_disable_step2();
vlock.fsm_sts = VLOCK_STATE_NULL;
if (vlock_disable_step2())
vlock.fsm_sts = VLOCK_STATE_NULL;
break;
default:
@@ -1672,6 +1837,9 @@ void vlock_process(struct vframe_s *vf)
if (probe_ok == 0 || !vlock_en)
return;
if (vlock_debug & VLOCK_DEBUG_FSM_DIS)
return;
/* todo:vlock processs only for tv chip */
if (vlock.dtdata->vlk_new_fsm)
vlock_fsm_monitor(vf);
@@ -1731,7 +1899,10 @@ void vlock_param_set(unsigned int val, enum vlock_param_e sel)
}
void vlock_status(void)
{
struct vinfo_s *vinfo;
pr_info("\n current vlock parameters status:\n");
pr_info("vlock driver version : %s\n", VLOCK_VER);
pr_info("vlock_mode:%d\n", vlock_mode);
pr_info("vlock_en:%d\n", vlock_en);
pr_info("vlock_adapt:%d\n", vlock_adapt);
@@ -1764,9 +1935,18 @@ void vlock_status(void)
pr_info("vlock_intput_type:%d\n", vlock_intput_type);
pr_info("vlock_pll_adj_limit:%d\n", vlock_pll_adj_limit);
pr_info("vlock_pll_val_last:%d\n", vlock_pll_val_last);
pr_info("vlk_support:%d\n", vlock.dtdata->vlk_support);
pr_info("vlk_new_fsm:%d\n", vlock.dtdata->vlk_new_fsm);
pr_info("vlock driver version : %s\n", VLOCK_VER);
pr_info("vlk_phlock_en:%d\n", vlock.dtdata->vlk_phlock_en);
pr_info("vlk_hwver:%d\n", vlock.dtdata->vlk_hwver);
vinfo = get_current_vinfo();
pr_info("vinfo sync_duration_num:%d\n", vinfo->sync_duration_num);
pr_info("vinfo sync_duration_den:%d\n", vinfo->sync_duration_den);
pr_info("vinfo video_clk:%d\n", vinfo->video_clk);
pr_info("vframe input_hz:%d\n", vlock.input_hz);
pr_info("vframe output_hz:%d\n", vlock.output_hz);
}
void vlock_reg_dump(void)
{
unsigned int addr;
@@ -1786,6 +1966,15 @@ void vlock_reg_dump(void)
amvecm_hiu_reg_read(HHI_HDMI_PLL_VLOCK_CNTL, &val);
pr_info("HIU [0x%04x]=0x%08x\n", HHI_HDMI_PLL_VLOCK_CNTL, val);
}
amvecm_hiu_reg_read(hhi_pll_reg_m, &val);
pr_info("HIU pll m[0x%04x]=0x%08x\n", hhi_pll_reg_m, val);
amvecm_hiu_reg_read(hhi_pll_reg_frac, &val);
pr_info("HIU pll f[0x%04x]=0x%08x\n", hhi_pll_reg_frac, val);
/*back up orignal pll value*/
pr_info("HIU pll m[0x%x]=0x%x\n", hhi_pll_reg_m, vlock.val_m);
pr_info("HIU pll f[0x%x]=0x%x\n", hhi_pll_reg_frac, vlock.val_frac);
}
/*work around method for vlock process hdmirx input interlace source.@20170803
**for interlace input,TOP and BOT have one line delta,

24
drivers/amlogic/media/enhancement/amvecm/vlock.h
View File

@@ -23,7 +23,7 @@
#include <linux/amlogic/media/vfm/vframe.h>
#include "linux/amlogic/media/amvecm/ve.h"
#define VLOCK_VER "Ref.2018/12/24"
#define VLOCK_VER "Ref.2019/1/24"
#define VLOCK_REG_NUM 33
@@ -69,7 +69,10 @@ struct stvlock_sig_sts {
u32 input_hz;
u32 output_hz;
bool md_support;
u32 phlock_percent;
struct vecm_match_data_s *dtdata;
u32 val_frac;
u32 val_m;
};
extern void amve_vlock_process(struct vframe_s *vf);
extern void amve_vlock_resume(void);
@@ -102,6 +105,10 @@ extern void vlock_log_print(void);
VLOCK_MODE_MANUAL_ENC | \
VLOCK_MODE_MANUAL_SOFT_ENC))
#define IS_AUTO_MODE(md) (md & \
(VLOCK_MODE_AUTO_PLL | \
VLOCK_MODE_AUTO_ENC))
#define IS_PLL_MODE(md) (md & \
(VLOCK_MODE_MANUAL_PLL | \
VLOCK_MODE_AUTO_PLL))
@@ -130,12 +137,13 @@ extern void vlock_log_print(void);
#define VLOCK_PLL_ADJ_LIMIT 9/*vlock pll adj limit(0x300a default)*/
/*vlock_debug mask*/
#define VLOCK_DEBUG_INFO (1 << 0)
#define VLOCK_DEBUG_FLUSH_REG_DIS (1 << 1)
#define VLOCK_DEBUG_ENC_LINE_ADJ_DIS (1 << 2)
#define VLOCK_DEBUG_ENC_PIXEL_ADJ_DIS (1 << 3)
#define VLOCK_DEBUG_AUTO_MODE_LOG_EN (1 << 4)
#define VLOCK_DEBUG_PLL2ENC_DIS (1 << 5)
#define VLOCK_DEBUG_INFO (0x1)
#define VLOCK_DEBUG_FLUSH_REG_DIS (0x2)
#define VLOCK_DEBUG_ENC_LINE_ADJ_DIS (0x4)
#define VLOCK_DEBUG_ENC_PIXEL_ADJ_DIS (0x8)
#define VLOCK_DEBUG_AUTO_MODE_LOG_EN (0x10)
#define VLOCK_DEBUG_PLL2ENC_DIS (0x20)
#define VLOCK_DEBUG_FSM_DIS (0x40)
/* 0:enc;1:pll;2:manual pll */
extern unsigned int vlock_mode;
@@ -161,4 +169,6 @@ extern int vlock_notify_callback(struct notifier_block *block,
extern void vlock_status_init(void);
extern void vlock_dt_match_init(struct vecm_match_data_s *pdata);
extern void vlock_set_en(bool en);
extern void vlock_set_phase(u32 percent);
extern void vlock_set_phase_en(u32 en);