From 51b493642cbb615de0708dce036aee89ad1078e6 Mon Sep 17 00:00:00 2001
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Date: Thu, 14 Nov 2024 16:33:30 +0000
Subject: [PATCH] drm/rockchip: debugfs: Add support for dclk rate count

Some chips support calculating the exact dclk frequencies,
adding debugfs support to read them.

Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Change-Id: I94ebb91e6a31de7ff6e2efa13f73e9108c6d297e
---
 .../gpu/drm/rockchip/rockchip_drm_debugfs.c   | 46 +++++++++++++++++++
 .../gpu/drm/rockchip/rockchip_drm_debugfs.h   |  7 +++
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h   |  1 +
 3 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c
index 8d71df1d4cbf..7b5e3c2bbe2f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.c
@@ -351,3 +351,49 @@ int rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *ro
 
 	return 0;
 }
+
+static int rockchip_drm_debugfs_dclk_rate_show(struct seq_file *s, void *data)
+{
+	struct drm_crtc *crtc = s->private;
+	struct rockchip_drm_private *priv = crtc->dev->dev_private;
+	int pipe = drm_crtc_index(crtc);
+	unsigned long rate;
+
+	if (!priv->crtc_funcs[pipe]->crtc_get_dclk_rate) {
+		seq_puts(s, "Not support get rate\n");
+		return 0;
+	}
+
+	rate = priv->crtc_funcs[pipe]->crtc_get_dclk_rate(crtc);
+
+	seq_printf(s, "%lu\n", rate);
+	return 0;
+}
+
+static int rockchip_drm_debugfs_dclk_rate_open(struct inode *inode, struct file *file)
+{
+	struct drm_crtc *crtc = inode->i_private;
+
+	return single_open(file, rockchip_drm_debugfs_dclk_rate_show, crtc);
+}
+
+static const struct file_operations rockchip_drm_debugfs_dclk_rate_ops = {
+	.owner = THIS_MODULE,
+	.open = rockchip_drm_debugfs_dclk_rate_open,
+	.read = seq_read,
+	.llseek = seq_lseek,
+	.release = single_release,
+};
+
+int rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root)
+{
+	struct dentry *ent;
+
+	ent = debugfs_create_file("calculated_dclk_rate", 0644, root, crtc,
+				  &rockchip_drm_debugfs_dclk_rate_ops);
+	if (!ent)
+		DRM_ERROR("Failed to add dclk_rate for debugfs\n");
+
+	return 0;
+}
+
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h
index 2f8ec1677245..bb7290146427 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_debugfs.h
@@ -37,6 +37,7 @@ rockchip_drm_crtc_dump_plane_buffer(struct drm_crtc *crtc)
 #endif
 int rockchip_drm_debugfs_add_color_bar(struct drm_crtc *crtc, struct dentry *root);
 int rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *root);
+int rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root);
 #else
 static inline int
 rockchip_drm_add_dump_buffer(struct drm_crtc *crtc, struct dentry *root)
@@ -61,6 +62,12 @@ rockchip_drm_debugfs_add_regs_write(struct drm_crtc *crtc, struct dentry *root)
 {
 	return 0;
 }
+
+static inline int
+rockchip_drm_debugfs_add_dclk_rate(struct drm_crtc *crtc, struct dentry *root)
+{
+	return 0;
+}
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index c28e84f7a2b1..1dc25364eed7 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -527,6 +527,7 @@ struct rockchip_crtc_funcs {
 	void (*crtc_output_post_enable)(struct drm_crtc *crtc, int intf);
 	void (*crtc_output_pre_disable)(struct drm_crtc *crtc, int intf);
 	int (*crtc_set_color_bar)(struct drm_crtc *crtc, enum rockchip_color_bar_mode mode);
+	unsigned long (*crtc_get_dclk_rate)(struct drm_crtc *crtc);
 	int (*set_aclk)(struct drm_crtc *crtc, enum rockchip_drm_vop_aclk_mode aclk_mode, struct dmcfreq_vop_info *vop_bw_info);
 	int (*get_crc)(struct drm_crtc *crtc);
 	void (*iommu_fault_handler)(struct drm_crtc *crtc, struct iommu_domain *iommu);