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audio: add 10ms delay before pdn enable [1/1]

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PD#SWPL-7680

Problem:
the pwn signal is self excitable

Solution:
1)add 10ms delay before pdn enable
2)set default clk for extern codec

Verify:
HW verify

Change-Id: I031b20851ee1eeb65215075fc8abe783ceddf42b
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
This commit is contained in:
Zhe Wang
2019-04-28 11:22:14 +08:00
committed by Tao Zeng
parent e2c536b481
commit 51d1794768
2 changed files with 30 additions and 1 deletions
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29
sound/soc/amlogic/auge/tdm.c
View File

@@ -1262,6 +1262,32 @@ static int aml_dai_tdm_mute_stream(struct snd_soc_dai *cpu_dai,
return 0;
}
static int aml_set_default_tdm_clk(struct aml_tdm *tdm)
{
unsigned int mclk = 12288000;
unsigned int ratio = aml_mpll_mclk_ratio(mclk);
unsigned int lrclk_hi;
/*set default i2s clk for codec sequence*/
tdm->setting.bclk_lrclk_ratio = 64;
tdm->setting.sysclk_bclk_ratio = 4;
tdm->clk_sel = 0;
lrclk_hi = tdm->setting.bclk_lrclk_ratio - 1;
aml_tdm_set_lrclkdiv(tdm->actrl, tdm->clk_sel,
tdm->setting.sysclk_bclk_ratio - 1);
aml_tdm_set_bclk_ratio(tdm->actrl,
tdm->clk_sel, lrclk_hi/2, lrclk_hi);
clk_prepare_enable(tdm->mclk);
clk_set_rate(tdm->clk, mclk*ratio);
clk_set_rate(tdm->mclk, mclk);
return 0;
}
static struct snd_soc_dai_ops aml_dai_tdm_ops = {
.prepare = aml_dai_tdm_prepare,
.trigger = aml_dai_tdm_trigger,
@@ -1556,6 +1582,9 @@ static int aml_tdm_platform_probe(struct platform_device *pdev)
/*return PTR_ERR(p_tdm->pin_ctl);*/
}
/*set default clk for output*/
aml_set_default_tdm_clk(p_tdm);
/* mclk pad ctrl */
ret = of_property_read_u32(node, "mclk_pad",
&p_tdm->mclk_pad);

2
sound/soc/codecs/amlogic/ad82584f.c
View File

@@ -773,7 +773,7 @@ static int reset_ad82584f_GPIO(struct snd_soc_codec *codec)
return -1;
gpio_direction_output(pdata->reset_pin, GPIOF_OUT_INIT_LOW);
mdelay(1);
mdelay(10);
gpio_direction_output(pdata->reset_pin, GPIOF_OUT_INIT_HIGH);
mdelay(1);