From 51db02c8647d3366f2fb0e6b96e41388a6dc8342 Mon Sep 17 00:00:00 2001 From: Elaine Zhang Date: Mon, 9 Nov 2020 16:11:18 +0800 Subject: [PATCH] clk: rockchip: rk3568: fix up the vop dclk setting error Signed-off-by: Elaine Zhang Change-Id: I629f699c133c2b395962321f2db9b5645f41c05a --- drivers/clk/rockchip/clk-rk3568.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c index 7546533f4b7d..7f4630cd6579 100644 --- a/drivers/clk/rockchip/clk-rk3568.c +++ b/drivers/clk/rockchip/clk-rk3568.c @@ -1058,15 +1058,15 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { RK3568_CLKGATE_CON(20), 8, GFLAGS), GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, RK3568_CLKGATE_CON(20), 9, GFLAGS), - COMPOSITE_DCLK(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 10, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE), - COMPOSITE_DCLK(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3568_CLKGATE_CON(20), 10, GFLAGS), + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 11, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE), - COMPOSITE_DCLK(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, + RK3568_CLKGATE_CON(20), 11, GFLAGS), + COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, - RK3568_CLKGATE_CON(20), 12, GFLAGS, RK3568_DCLK_PARENT_MAX_PRATE), + RK3568_CLKGATE_CON(20), 12, GFLAGS), GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, RK3568_CLKGATE_CON(20), 13, GFLAGS), GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo", 0,