From 52439761bfb055ca3786d4904a240ebf361504b9 Mon Sep 17 00:00:00 2001 From: Guochun Huang Date: Wed, 8 Dec 2021 19:32:37 +0800 Subject: [PATCH] phy: rockchip: mipi-dcphy: fix PLL VCO restrictions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Frequency of VCO's output: 2600MHz ≤ Fvco ≤ 6600MHz Signed-off-by: Guochun Huang Change-Id: Iace886293b9d30d0cedcae4ad56582109c5ee716 --- drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c index 91e60ad58472..3651cc850eae 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c @@ -1466,7 +1466,11 @@ samsung_mipi_dcphy_pll_round_rate(struct samsung_mipi_dcphy *samsung, /* 0 ≤ S[2:0] ≤ 6 */ for (_scaler = 0; _scaler < 7; _scaler++) { fvco = fout << _scaler; - if (fvco > max_fout) + + /* + * 2600MHz ≤ FVCO ≤ 6600MHz + */ + if (fvco < 2600 || fvco > 6600) continue; /* 6MHz ≤ Fref(Fin / p) ≤ 30MHz */