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drm/amdgpu: Match against exact bootloader status

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[ Upstream commit d3de41ee5f ]

On PSP v13.x ASICs, boot loader will set only the MSB to 1 and clear the
least significant bits for any command submission. Hence match against
the exact register value, otherwise a register value of all 0xFFs also
could falsely indicate that boot loader is ready. Also, from PSP v13.0.6
and newer, bits[7:0] will be used to indicate command error status.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Lijo Lazar
2023-07-25 19:11:54 +05:30
committed by Greg Kroah-Hartman
parent f20bee49dc
commit 5251c83532
1 changed files with 8 additions and 7 deletions
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15
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
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@@ -147,14 +147,15 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
int ret; int ret;
int retry_loop; int retry_loop;
/* Wait for bootloader to signify that it is ready having bit 31 of
* C2PMSG_35 set to 1. All other bits are expected to be cleared.
* If there is an error in processing command, bits[7:0] will be set.
* This is applicable for PSP v13.0.6 and newer.
*/
for (retry_loop = 0; retry_loop < 10; retry_loop++) { for (retry_loop = 0; retry_loop < 10; retry_loop++) {
/* Wait for bootloader to signify that is ret = psp_wait_for(
ready having bit 31 of C2PMSG_35 set to 1 */ psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
ret = psp_wait_for(psp, 0x80000000, 0xffffffff, false);
SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
0x80000000,
0x80000000,
false);
if (ret == 0) if (ret == 0)
return 0; return 0;