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dts: tvafe: update cutwindow for tl1 [1/1]

Browse Source 
PD#SWPL-8866

Problem:
atv line freq adjust is not qualified

Solution:
update cutwindow

Verify:
x301

Change-Id: Iaeaa2fbf27db22ad17ef2700e70f7af424a2539a
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
This commit is contained in:
Evoke Zhang
2019-06-03 11:28:28 +08:00
committed by Tao Zeng
parent 256ef2624c
commit 52b05ba04b
8 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
View File

@@ -630,8 +630,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
/* auto_adj_en:
* bit0 -- auto cdto
* bit1 -- auto hs

4
arch/arm/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
View File

@@ -625,8 +625,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
/* auto_adj_en:
* bit0 -- auto cdto
* bit1 -- auto hs

4
arch/arm/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -624,8 +624,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
};
vbi {

4
arch/arm/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -624,8 +624,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
};
vbi {

4
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_1g.dts
View File

@@ -627,8 +627,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
/* auto_adj_en:
* bit0 -- auto cdto
* bit1 -- auto hs

4
arch/arm64/boot/dts/amlogic/tl1_t962x2_x301_2g.dts
View File

@@ -621,8 +621,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
/* auto_adj_en:
* bit0 -- auto cdto
* bit1 -- auto hs

4
arch/arm64/boot/dts/amlogic/tm2_t962e2_ab311.dts
View File

@@ -620,8 +620,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
};
vbi {

4
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
View File

@@ -622,8 +622,8 @@
clocks = <&clkc CLKID_DAC_CLK>;
clock-names = "vdac_clk_gate";
cutwindow_val_h = <0 10 18 20 62>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
cutwindow_val_h = <0 0 0 0 8>; /* level 0~4 */
cutwindow_val_v = <4 8 14 16 24>; /* level 0~4 */
};
vbi {