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UPSTREAM: ARM: 9267/1: Define Armv8 registers in AArch32 state

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AArch32 Instruction Set Attribute Register 6 (ID_ISAR6_EL1) and AArch32
Processor Feature Register 2 (ID_PFR2_EL1) identifies some new features
for the Armv8 architecture. This registers will be utilized to add
hwcaps for those cpu features.

These registers are marked as reserved for Armv7 and should be a RAZ.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>

Bug: 282663915
(cherry picked from commit 74c344e6f1)
Change-Id: I5545dbb3d22424ef130c0f95e92ee31a9e7de9be
Signed-off-by: Mark-PK Tsai <mark-pk.tsai@mediatek.com>
This commit is contained in:
Amit Daniel Kachhap
2022-11-17 06:16:12 +01:00
committed by Todd Kjos
parent a6f12f29b8
commit 52e28a12a9
1 changed files with 4 additions and 0 deletions
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4
arch/arm/include/asm/cputype.h
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@@ -25,6 +25,8 @@
#define CPUID_EXT_ISAR3 0x6c
#define CPUID_EXT_ISAR4 0x70
#define CPUID_EXT_ISAR5 0x74
#define CPUID_EXT_ISAR6 0x7c
#define CPUID_EXT_PFR2 0x90
#else
#define CPUID_EXT_PFR0 "c1, 0"
#define CPUID_EXT_PFR1 "c1, 1"
@@ -40,6 +42,8 @@
#define CPUID_EXT_ISAR3 "c2, 3"
#define CPUID_EXT_ISAR4 "c2, 4"
#define CPUID_EXT_ISAR5 "c2, 5"
#define CPUID_EXT_ISAR6 "c2, 7"
#define CPUID_EXT_PFR2 "c3, 4"
#endif
#define MPIDR_SMP_BITMASK (0x3 << 30)