From 530d2fa7935e5d9aae4c3e4a6da86d3dfb250306 Mon Sep 17 00:00:00 2001 From: Zhang Yubing Date: Tue, 29 Mar 2022 09:20:01 +0800 Subject: [PATCH] drm/rockchip: vop2: get hdmi phy clk rate rate before set hdmi phy clk rate may change by hdmi controller, while clk framework don't know that, whick may set wrong dclk rate when use hdmi phy pll as dclk parent. So It necessary to update the hdmi phy pll clk rate before set a new clk rate. Signed-off-by: Zhang Yubing Change-Id: I4ca6d5e34f0459ecbcfa894e9a136d05408160a0 --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index cc91258d84f9..7f90b080efbf 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -3608,6 +3608,11 @@ static int vop2_clk_set_parent_extend(struct vop2_video_port *vp, hdmi0_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi0_phy_pll"); hdmi1_phy_pll = vop2_extend_clk_find_by_name(vop2, "hdmi1_phy_pll"); + if (hdmi0_phy_pll) + clk_get_rate(hdmi0_phy_pll->clk); + if (hdmi1_phy_pll) + clk_get_rate(hdmi1_phy_pll->clk); + if ((!hdmi0_phy_pll && !hdmi1_phy_pll) || ((vcstate->output_if & VOP_OUTPUT_IF_HDMI0) && !hdmi0_phy_pll) || ((vcstate->output_if & VOP_OUTPUT_IF_HDMI1) && !hdmi1_phy_pll))