From 53ca3ac1f0a092b6350551cf297779e4028c1519 Mon Sep 17 00:00:00 2001 From: chenxing Date: Mon, 13 May 2013 10:15:39 +0800 Subject: [PATCH] rk30xx: add lpj_gpll init to prevent dma halt and sdio error --- arch/arm/mach-rk30/clock_data-rk3066b.c | 2 ++ arch/arm/mach-rk30/clock_data.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/mach-rk30/clock_data-rk3066b.c b/arch/arm/mach-rk30/clock_data-rk3066b.c index abf66390fcdf..66a2006b6957 100644 --- a/arch/arm/mach-rk30/clock_data-rk3066b.c +++ b/arch/arm/mach-rk30/clock_data-rk3066b.c @@ -3298,6 +3298,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long //general clk_set_rate_nolock(&general_pll_clk, gpll_rate); + lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate); + //code pll clk_set_rate_nolock(&codec_pll_clk, cpll_rate); diff --git a/arch/arm/mach-rk30/clock_data.c b/arch/arm/mach-rk30/clock_data.c index 0b5a39b529db..5643b48e27ab 100644 --- a/arch/arm/mach-rk30/clock_data.c +++ b/arch/arm/mach-rk30/clock_data.c @@ -3342,6 +3342,8 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate,unsigned long clk_set_rate_nolock(&general_pll_clk, 297 * MHZ); #endif clk_set_rate_nolock(&general_pll_clk, gpll_rate); + lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate); + //code pll clk_set_rate_nolock(&codec_pll_clk, cpll_rate);