From 54649eec2bf21a5af11ef7064aa44cdb5df42dee Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 8 Jun 2021 17:18:37 +0800 Subject: [PATCH] phy: phy-rockchip-snps-pcie3: Add sram_init_done check From test, sram_init_done can be used as a indicator to see if phy power and input clock work find. Let's yell out error is anything wrong with phy. Signed-off-by: Shawn Lin Change-Id: I5493e32ec5a9a6a8f6fc45e95618a657d9a21a67 --- drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c index 45144ee73214..999a4cafcf24 100644 --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c @@ -22,6 +22,8 @@ #define GRF_PCIE30PHY_CON1 0x4 #define GRF_PCIE30PHY_CON6 0x18 #define GRF_PCIE30PHY_CON9 0x24 +#define GRF_PCIE30PHY_STATUS0 0x80 +#define SRAM_INIT_DONE(reg) (reg & BIT(14)) struct rockchip_p3phy_priv { void __iomem *mmio; @@ -62,6 +64,7 @@ static int rochchip_p3phy_init(struct phy *phy) { struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); int ret; + u32 reg; ret = clk_prepare_enable(priv->ref_clk_m); if (ret < 0) @@ -91,6 +94,16 @@ static int rochchip_p3phy_init(struct phy *phy) reset_control_deassert(priv->p30phy); + ret = regmap_read_poll_timeout(priv->phy_grf, + GRF_PCIE30PHY_STATUS0, + reg, SRAM_INIT_DONE(reg), + 0, 500); + if (ret) { + pr_err("%s: lock failed 0x%x, check input refclk and power supply\n", + __func__, reg); + goto err_pclk; + } + return 0; err_pclk: clk_disable_unprepare(priv->ref_clk_n);