diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index f74775464357..3fd603febdf3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -1549,20 +1549,27 @@ static void vop2_load_sdr2hdr_table(struct vop2_video_port *vp, int sdr2hdr_tf)
 	const struct vop2_video_port_regs *regs = vp->regs;
 	uint32_t sdr2hdr_eotf_oetf_yn[65];
 	uint32_t sdr2hdr_oetf_dx_dxpow[64];
-	int i;
+	int i, bt1886_eotf_coe = 1;
 
 	for (i = 0; i < 65; i++) {
+		/*
+		 * rk3568/rk3588 sdr2hdr bt1886 eotf dx << 1 by mistake, so add
+		 * bt1886_eotf_coe to adapt it.
+		 */
+		if (i == 64)
+			bt1886_eotf_coe = 0;
+
 		if (sdr2hdr_tf == SDR2HDR_FOR_BT2020)
 			sdr2hdr_eotf_oetf_yn[i] =
-				table->sdr2hdr_bt1886eotf_yn_for_bt2020[i] +
+				(table->sdr2hdr_bt1886eotf_yn_for_bt2020[i] << bt1886_eotf_coe) +
 				(table->sdr2hdr_st2084oetf_yn_for_bt2020[i] << 18);
 		else if (sdr2hdr_tf == SDR2HDR_FOR_HDR)
 			sdr2hdr_eotf_oetf_yn[i] =
-				table->sdr2hdr_bt1886eotf_yn_for_hdr[i] +
+				(table->sdr2hdr_bt1886eotf_yn_for_hdr[i] << bt1886_eotf_coe) +
 				(table->sdr2hdr_st2084oetf_yn_for_hdr[i] << 18);
 		else if (sdr2hdr_tf == SDR2HDR_FOR_HLG_HDR)
 			sdr2hdr_eotf_oetf_yn[i] =
-				table->sdr2hdr_bt1886eotf_yn_for_hlg_hdr[i] +
+				(table->sdr2hdr_bt1886eotf_yn_for_hlg_hdr[i] << bt1886_eotf_coe) +
 				(table->sdr2hdr_st2084oetf_yn_for_hlg_hdr[i] << 18);
 	}
 
@@ -11070,7 +11077,7 @@ static void vop2_setup_hdr10(struct vop2_video_port *vp, uint8_t win_phys_id)
 	bool sdr2hdr_en = 0;
 	bool sdr2hdr_tf = 0;
 	bool hdr2sdr_tf_update = 1;
-	bool sdr2hdr_tf_update = 0; /* default sdr2hdr curve is 1000 nit */
+	bool sdr2hdr_tf_update = 1;
 	unsigned long win_mask = vp->win_mask;
 	int phys_id;
 	bool have_sdr_layer = false;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
index 1651d719852c..2c4957ad8100 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
@@ -415,24 +415,24 @@ static const u32 sdr2hdr_bt1886eotf_yn_for_bt2020[65] = {
 };
 
 static u32 sdr2hdr_bt1886eotf_yn_for_hdr[65] = {
-	/* dst_range 425int */
+	/* dst_range 500 nit */
 	0,
-	5,     21,    49,     91,
-	150,   225,   320,   434,
-	569,   726,   905,   1108,
-	1336,  1588,  1866,  2171,
-	2502,  2862,  3250,  3667,
-	3887,  4114,  4349,  4591,
-	4841,  5099,  5364,  5638,
-	5920,  6209,  6507,  6812,
-	6968,  7126,  7287,  7449,
-	7613,  7779,  7948,  8118,
-	8291,  8466,  8643,  8822,
-	9003,  9187,  9372,  9560,
-	9655,  9750,  9846,  9942,
-	10039, 10136, 10234, 10333,
-	10432, 10531, 10631, 10732,
-	10833, 10935, 11038, 11141,
+	6,     29,    72,    135,
+	221,   330,   463,   621,
+	804,   1014,  1251,  1515,
+	1807,  2126,  2475,  2853,
+	3260,  3696,  4163,  4661,
+	4921,  5189,  5464,  5748,
+	6039,  6338,  6646,  6961,
+	7284,  7615,  7954,  8301,
+	8477,  8656,  8837,  9019,
+	9204,  9391,  9580,  9771,
+	9964,  10159, 10356, 10555,
+	10756, 10959, 11165, 11372,
+	11477, 11582, 11687, 11793,
+	11900, 12007, 12115, 12223,
+	12332, 12441, 12551, 12661,
+	12772, 12883, 12995, 13107,
 };
 
 static const u32 sdr2hdr_st2084oetf_yn_for_hlg_hdr[65] = {