From 54f2fcc787e5e77d9f6b716a8faf316301fd04cc Mon Sep 17 00:00:00 2001 From: Wyon Bi Date: Tue, 8 Feb 2022 17:42:05 +0800 Subject: [PATCH] arm64: dts: rockchip: rk3568: Add edp phy grf node Signed-off-by: Wyon Bi Change-Id: I0ee522627cc057bd5b0be2c862e56f020dae57a2 --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index fbd15c22072d..7042546a0b94 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -787,15 +787,18 @@ reg = <0x0 0xfdca8000 0x0 0x8000>; }; - edp_phy: edp-phy@fdcb0000 { - compatible = "rockchip,rk3568-edp-phy"; - reg = <0x0 0xfdcb0000 0x0 0x8000>; - clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>; - clock-names = "refclk", "pclk"; - resets = <&cru SRST_P_EDPPHY_GRF>; - reset-names = "apb"; - #phy-cells = <0>; - status = "disabled"; + edp_phy_grf: syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdcb0000 0x0 0x100>; + clocks = <&cru PCLK_EDPPHY_GRF>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3568-edp-phy"; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>; + clock-names = "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; }; pcie30_phy_grf: syscon@fdcb8000 {