From 5500eb5ebfed0d4241eebca143b7d414fc23804a Mon Sep 17 00:00:00 2001
From: Elaine Zhang <zhangqing@rock-chips.com>
Date: Sun, 7 Oct 2018 18:20:12 +0800
Subject: [PATCH] arm64: dts: rockchip: enable power domain for rk1808

fix up the pd_pcie clks.
add power-domains = <&power RK1808_PD_PCIE> for usb host.
enable power status.

Change-Id: I040c3c24ab542add96f87ca7b2453b60703b2a4d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk1808.dtsi | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk1808.dtsi b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
index 95eba32777d1..39d27815e65c 100644
--- a/arch/arm64/boot/dts/rockchip/rk1808.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk1808.dtsi
@@ -447,7 +447,7 @@
 			#power-domain-cells = <1>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			status = "disabled";
+			status = "okay";
 
 			/* These power domains are grouped by VD_NPU */
 			pd_npu@RK1808_VD_NPU {
@@ -467,7 +467,13 @@
 					 <&cru ACLK_PCIE_MST>,
 					 <&cru ACLK_PCIE_SLV>,
 					 <&cru PCLK_PCIE>,
-					 <&cru SCLK_PCIE_AUX>;
+					 <&cru SCLK_PCIE_AUX>,
+					 <&cru SCLK_PCIE_AUX>,
+					 <&cru ACLK_USB3OTG>,
+					 <&cru HCLK_HOST>,
+					 <&cru HCLK_HOST_ARB>,
+					 <&cru SCLK_USB3_OTG0_REF>,
+					 <&cru SCLK_USB3_OTG0_SUSPEND>;
 				pm_qos = <&qos_pcie>;
 			};
 			pd_vpu@RK1808_PD_VPU {
@@ -1094,6 +1100,7 @@
 		phys = <&u2phy_host>;
 		phy-names = "usb";
 		status = "disabled";
+		power-domains = <&power RK1808_PD_PCIE>;
 	};
 
 	usb_host0_ohci: usb@ffd90000 {
@@ -1106,6 +1113,7 @@
 		phys = <&u2phy_host>;
 		phy-names = "usb";
 		status = "disabled";
+		power-domains = <&power RK1808_PD_PCIE>;
 	};
 
 	gmac: ethernet@ffdd0000 {