From 3f38eabc5b585c1afdb74f848fc46147c12b08d6 Mon Sep 17 00:00:00 2001 From: Huibin Hong Date: Wed, 30 Apr 2025 14:41:57 +0800 Subject: [PATCH 1/6] arm64: armv8_deprecated: protect prev_mode or it would cause undef_lock deadlock When do 'echo 1 > /proc/sys/abi/swp' on two cpus at the same time, we can see: call_undef_hook() at traps.c:442 do_undefinstr() at traps.c:504 el0_undef() at entry-common.c:605 el0t_64_sync_handler() at entry-common.c:689 el0t_64_sync() at entry.S:585 That is because write swp 1 at the same time, add the swp_hooks to the undef_hook list twice, swp_hooks list node's next becomes itself. When list_for_each_entry of the undef_hook, cpu loops forever here. Change-Id: Ice60dbc633020220e7218a554e9d0e4c7dacceb4 Signed-off-by: Huibin Hong --- arch/arm64/kernel/armv8_deprecated.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c index fb0e7c7b2e20..9ca9892a6e39 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c @@ -209,9 +209,10 @@ static int emulation_proc_handler(struct ctl_table *table, int write, { int ret = 0; struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode); - enum insn_emulation_mode prev_mode = insn->current_mode; + enum insn_emulation_mode prev_mode; mutex_lock(&insn_emulation_mutex); + prev_mode = insn->current_mode; ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); if (ret || !write || prev_mode == insn->current_mode) From 8d47fabe2f1cad9d7f2514a83a853433b329581b Mon Sep 17 00:00:00 2001 From: Wu Liangqing Date: Wed, 23 Apr 2025 15:35:31 +0800 Subject: [PATCH 2/6] arm64: dts: rockchip: add rk3588-evb10-v10.dts for rk3588 evb10 Change-Id: I83775b3c362c954b8d3551b48f543c53f775c0bf Signed-off-by: Wu Liangqing --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3588-evb10-v10-imx415.dtsi | 167 +++ .../dts/rockchip/rk3588-evb10-v10-linux.dts | 16 + .../boot/dts/rockchip/rk3588-evb10-v10.dts | 16 + .../arm64/boot/dts/rockchip/rk3588-evb10.dtsi | 971 ++++++++++++++++++ 5 files changed, 1172 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-imx415.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-linux.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb10-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index e7ce8f8dfd6c..87301a37ecfe 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -334,6 +334,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v11-linux-ipc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-rk628-hdmi2csi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb10-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb10-v10-linux.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-imx415.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-imx415.dtsi new file mode 100644 index 000000000000..0d071f0f8b62 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-imx415.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipidphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidphy0_pwr>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidphy0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&pinctrl { + cam { + mipidphy0_pwr: mipidphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-linux.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-linux.dts new file mode 100644 index 000000000000..26db2dd2a5d2 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10-linux.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb10.dtsi" +#include "rk3588-evb10-v10-imx415.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB10 V10 Board"; + compatible = "rockchip,rk3588-evb10-v10", "rockchip,rk3588"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10.dts new file mode 100644 index 000000000000..0a0bef470c37 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb10-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb10.dtsi" +#include "rk3588-evb10-v10-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB10 V10 Board"; + compatible = "rockchip,rk3588-evb10-v10", "rockchip,rk3588"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi new file mode 100644 index 000000000000..7040968053c0 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb10.dtsi @@ -0,0 +1,971 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (256 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,pre-power-on-delay-ms = <30>; + rockchip,post-power-down-delay-ms = <40>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pciem1: vcc3v3-pciem1 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pciem1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pciem2: vcc3v3-pciem2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pciem2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pciem3: vcc3v3-pciem3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pciem3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm1 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1m0_pins>; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c5m3_xfer { + rockchip,pins = + /* i2c5_scl_m3 */ + <1 RK_PB6 9 &pcfg_pull_up>, + /* i2c5_sda_m3 */ + <1 RK_PB7 9 &pcfg_pull_up>; +}; + +&i2c6 { + status = "okay"; + + usbc0: husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-0 = <&i2c8m4_xfer>; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + icm42607_acc: icm_acc@68 { + status = "okay"; + compatible = "icm42607_acc"; + reg = <0x68>; + irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + }; + + icm42607_gyro: icm_gyro@68 { + status = "okay"; + compatible = "icm42607_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + phys = <&pcie30phy>; + vpcie3v3-supply = <&vcc3v3_pciem3>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pciem1>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pciem2>; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_leds_gpio: work-leds-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + status = "disabled"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&work_led { + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&work_leds_gpio>; +}; From 8b2e37f03c7a5ebaa443fa53702149221cc8666b Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Thu, 20 Feb 2025 11:05:36 +0000 Subject: [PATCH 3/6] drm/rockchip: vop2: Fix integer underflow for power domain ref_count If the PD has already been turned off, and the value of vop2_power_domain.ref_count is zero at this time, calling vop2_power_domain_put() again will cause ref_count to underflow. This underflow will be interpreted as if the PD has been turned on. Fixes: aa3aee14d0ec ("drm/rockchip: vop2: Add vop2 internal pd support for rk3588") Change-Id: Ia814c5907072cd1aee785734e36053cba7382b23 Signed-off-by: Chaoyi Chen --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 02f4cc262046..12d20d51ea42 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2067,11 +2067,14 @@ static void vop2_power_domain_put(struct vop2_power_domain *pd) * * So we have a check here */ - if (--pd->ref_count == 0 && vop2_power_domain_can_off_by_vsync(pd)) { - if (pd->vop2->data->delayed_pd) - schedule_delayed_work(&pd->power_off_work, msecs_to_jiffies(2500)); - else - vop2_power_domain_off(pd); + if (pd->ref_count) { + pd->ref_count--; + if (pd->ref_count == 0 && vop2_power_domain_can_off_by_vsync(pd)) { + if (pd->vop2->data->delayed_pd) + schedule_delayed_work(&pd->power_off_work, msecs_to_jiffies(2500)); + else + vop2_power_domain_off(pd); + } } spin_unlock(&pd->lock); From ce5794977b04458fe6b032923a732bb8c6600f09 Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Fri, 21 Feb 2025 01:59:38 +0000 Subject: [PATCH 4/6] drm/rockchip: vop2: Set initial ref_count for parent power domain If the power domain has a parent power domain, the ref_count of parent power domain should also be set during initialization. Change-Id: I4948d11fee2829049559541040ae2117ca319329 Signed-off-by: Chaoyi Chen --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 12d20d51ea42..ffc24387ea83 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -7804,6 +7804,7 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) struct vop2_extend_pll *ext_pll; struct clk *parent_clk; const char *clk_name; + struct vop2_power_domain *pd; if (on == vp->loader_protect) return 0; @@ -7817,9 +7818,11 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) if (crtc->primary) { win = to_vop2_win(crtc->primary); if (VOP_WIN_GET(vop2, win, enable)) { - if (win->pd) { - win->pd->ref_count++; - win->pd->vp_mask |= BIT(vp->id); + pd = win->pd; + while (pd) { + pd->ref_count++; + pd->vp_mask |= BIT(vp->id); + pd = pd->parent; } vp->enabled_win_mask |= BIT(win->phys_id); @@ -7841,8 +7844,12 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) if (splice_win->pd && VOP_WIN_GET(vop2, splice_win, enable)) { - splice_win->pd->ref_count++; - splice_win->pd->vp_mask |= BIT(splice_vp->id); + pd = splice_win->pd; + while (pd) { + pd->ref_count++; + pd->vp_mask |= BIT(splice_vp->id); + pd = pd->parent; + } } } } From 1f34b60222e1540bf72778efe5c344c074c367e5 Mon Sep 17 00:00:00 2001 From: Chaoyi Chen Date: Sat, 22 Feb 2025 07:55:23 +0000 Subject: [PATCH 5/6] drm/rockchip: vop2: Use regbak to determine whether win is disabled The vop2_win_disable() may be called multiple times in a short period before the fs comes. Using VOP_WIN_GET(vop2, win, enable) for judgment may cause double disable of win, leading to double decrement of vop2_power_domain.ref_count. This patch uses regbak to determine whether win is already disabled in vop2_win_disable(), similar to what is done in the vop2_win_enable(). Change-Id: I3095ef0ef0068ef3dd7245375127083a17871341 Signed-off-by: Chaoyi Chen --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index ffc24387ea83..46bbd657c764 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -2181,7 +2181,7 @@ static void vop2_win_disable(struct vop2_win *win, bool skip_splice_win) win->splice_win = NULL; } - if (VOP_WIN_GET(vop2, win, enable) || VOP_WIN_GET_REG_BAK(vop2, win, enable)) { + if (VOP_WIN_GET_REG_BAK(vop2, win, enable)) { VOP_WIN_SET(vop2, win, enable, 0); /* * at rk3576 platform, the esmart1/3 can merge from vp1, but the enable bit: port0_extra_alpha_en @@ -7818,6 +7818,8 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) if (crtc->primary) { win = to_vop2_win(crtc->primary); if (VOP_WIN_GET(vop2, win, enable)) { + /* set enable in regbaks */ + VOP_WIN_SET(vop2, win, enable, 1); pd = win->pd; while (pd) { pd->ref_count++; @@ -7844,6 +7846,8 @@ static int vop2_crtc_loader_protect(struct drm_crtc *crtc, bool on, void *data) if (splice_win->pd && VOP_WIN_GET(vop2, splice_win, enable)) { + /* set enable in regbaks */ + VOP_WIN_SET(vop2, splice_win, enable, 1); pd = splice_win->pd; while (pd) { pd->ref_count++; From 5c295c7639743d1dcff31322281ebe283e0e20f0 Mon Sep 17 00:00:00 2001 From: Sandy Huang Date: Tue, 8 Apr 2025 16:46:47 +0800 Subject: [PATCH 6/6] drm/rockchip: vop2: avoid config done time close to vsync Avoid commit new plane time close to vsync at async mode, the following case maybe lead to error: vsync[1]->update plane[2]->config done[3]->update plane[4]->vsync[5] If new vsync[5] insert step 4, only part of plane register complete, this will lead to part of plane register take effect and lead to error. So we introduce this safeguard, when commit time exceeds 15/16 of a frame, this frame will be postponed to the next frame. Signed-off-by: Sandy Huang Change-Id: I4e405baf6ac080f6990e94f639c168ff9f0daf1c --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 46bbd657c764..b9de39ca740a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1084,6 +1084,12 @@ static inline void rk3588_vop2_dsc_cfg_done(struct drm_crtc *crtc); static inline void vop2_cfg_done(struct drm_crtc *crtc); static void vop2_wait_for_fs_by_done_bit_status(struct vop2_video_port *vp); static int vop2_clk_reset(struct reset_control *rstc); +static void vop2_wait_for_scan_timing_max_to_assigned_line(struct vop2_video_port *vp, + u32 current_line, + u32 wait_line); +static void vop2_wait_for_scan_timing_from_the_assigned_line(struct vop2_video_port *vp, + u32 current_line, + u32 wait_line); static inline struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) { @@ -12555,6 +12561,25 @@ static void vop2_crtc_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_stat goto out; } + /* + * Avoid commit new plane time close to vsync at async mode, the + * following case maybe lead to error: + * vsync[1] -> update plane[2] -> config done[3] -> update plane[4] -> vsync[5] + * If new vsync[5] insert step 4, only part of plane register complete, + * this will lead to part of plane register take effect and lead to error. + * + * So we introduce this safeguard, when commit time exceeds 15/16 of a frame, + * this commit will be postponed to the next frame. + */ + if (state->legacy_cursor_update) { + u16 vtotal = VOP_MODULE_GET(vop2, vp, dsp_vtotal); + u32 assigned_line = vtotal * 15 >> 4; + u32 current_line = vop2_read_vcnt(vp); + + if (current_line > assigned_line) + vop2_wait_for_scan_timing_max_to_assigned_line(vp, current_line, assigned_line); + } + if (vop2->version == VOP_VERSION_RK3588) vop2_crtc_update_vrr(crtc);