diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 60065779f076..b6db520fb768 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -1255,8 +1255,12 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, /* now create the actual pll */ init.name = pll_name; +#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE /* keep all plls untouched for now */ init.flags = flags | CLK_IGNORE_UNUSED; +#else + init.flags = flags; +#endif init.parent_names = &parent_names[0]; init.num_parents = 1; diff --git a/drivers/clk/rockchip/clk-rv1126.c b/drivers/clk/rockchip/clk-rv1126.c index f5d59544ab41..dadb5030359e 100644 --- a/drivers/clk/rockchip/clk-rv1126.c +++ b/drivers/clk/rockchip/clk-rv1126.c @@ -65,7 +65,11 @@ static struct rockchip_pll_rate_table rv1126_pll_rates[] = { RK3036_PLL_RATE(700000000, 3, 350, 4, 1, 1, 0), RK3036_PLL_RATE(696000000, 1, 116, 4, 1, 1, 0), RK3036_PLL_RATE(624000000, 1, 104, 4, 1, 1, 0), +#ifdef CONFIG_ROCKCHIP_LOW_PERFORMANCE + RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0), +#else RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), +#endif RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), RK3036_PLL_RATE(504000000, 1, 84, 4, 1, 1, 0), RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), @@ -142,7 +146,6 @@ static const struct rockchip_cpuclk_reg_data rv1126_cpuclk_data = { PNAME(mux_pll_p) = { "xin24m" }; PNAME(mux_rtc32k_p) = { "clk_pmupvtm_divout", "xin32k", "clk_osc0_div32k" }; PNAME(mux_wifi_p) = { "clk_wifi_osc0", "clk_wifi_div" }; -PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" }; PNAME(mux_uart1_p) = { "sclk_uart1_div", "sclk_uart1_fracdiv", "xin24m" }; PNAME(mux_xin24m_gpll_p) = { "xin24m", "gpll" }; PNAME(mux_gpll_xin24m_p) = { "gpll", "xin24m" }; @@ -151,17 +154,12 @@ PNAME(mux_usbphy_otg_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_otg" }; PNAME(mux_usbphy_host_ref_p) = { "clk_ref12m", "xin_osc0_div2_usbphyref_host" }; PNAME(mux_mipidsiphy_ref_p) = { "clk_ref24m", "xin_osc0_mipiphyref" }; PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "clk_rtc32k" }; -PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" }; -PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" }; -PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; PNAME(mux_hclk_pclk_pdbus_p) = { "gpll", "dummy_cpll" }; -PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" }; PNAME(mux_uart0_p) = { "sclk_uart0_div", "sclk_uart0_frac", "xin24m" }; PNAME(mux_uart2_p) = { "sclk_uart2_div", "sclk_uart2_frac", "xin24m" }; PNAME(mux_uart3_p) = { "sclk_uart3_div", "sclk_uart3_frac", "xin24m" }; PNAME(mux_uart4_p) = { "sclk_uart4_div", "sclk_uart4_frac", "xin24m" }; PNAME(mux_uart5_p) = { "sclk_uart5_div", "sclk_uart5_frac", "xin24m" }; -PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" }; PNAME(mux_i2s0_tx_p) = { "mclk_i2s0_tx_div", "mclk_i2s0_tx_fracdiv", "i2s0_mclkin", "xin12m" }; PNAME(mux_i2s0_rx_p) = { "mclk_i2s0_rx_div", "mclk_i2s0_rx_fracdiv", "i2s0_mclkin", "xin12m" }; PNAME(mux_i2s0_tx_out2io_p) = { "mclk_i2s0_tx", "xin12m" }; @@ -170,13 +168,9 @@ PNAME(mux_i2s1_p) = { "mclk_i2s1_div", "mclk_i2s1_fracdiv", "i2s1_mclkin", "xi PNAME(mux_i2s1_out2io_p) = { "mclk_i2s1", "xin12m" }; PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xin12m" }; PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" }; -PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" }; -PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" }; -PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" }; PNAME(mux_aclk_pdvi_p) = { "aclk_pdvi_div", "aclk_pdvi_np5" }; -PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" }; PNAME(mux_clk_isp_p) = { "clk_isp_div", "clk_isp_np5" }; PNAME(mux_gpll_usb480m_p) = { "gpll", "usb480m" }; PNAME(mux_cif_out2io_p) = { "xin24m", "clk_cif_out2io_div", "clk_cif_out2io_fracdiv" }; @@ -191,24 +185,50 @@ PNAME(mux_rgmii_clk_p) = { "clk_gmac_tx_div50", "clk_gmac_tx_div5", "clk_gmac_ PNAME(mux_rmii_clk_p) = { "clk_gmac_rx_div20", "clk_gmac_rx_div2" }; PNAME(mux_gmac_tx_rx_p) = { "rgmii_mode_clk", "rmii_mode_clk" }; PNAME(mux_dpll_gpll_p) = { "dpll", "gpll" }; -PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" }; PNAME(mux_aclk_pdnpu_p) = { "aclk_pdnpu_div", "aclk_pdnpu_np5" }; PNAME(mux_clk_npu_p) = { "clk_npu_div", "clk_npu_np5" }; + +#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE +PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" }; +PNAME(mux_armclk_p) = { "gpll", "cpll", "apll" }; +PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "cpll", "dummy_dpll" }; +PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" }; +PNAME(mux_cpll_gpll_p) = { "cpll", "gpll" }; +PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(mux_cpll_hpll_gpll_p) = { "cpll", "hpll", "gpll" }; +PNAME(mux_cpll_gpll_hpll_p) = { "cpll", "gpll", "hpll" }; +PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "cpll", "hpll" }; +PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "cpll", "dummy_apll", "hpll" }; +#else +PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "dummy_cpll", "xin24m" }; +PNAME(mux_armclk_p) = { "gpll", "dummy_cpll", "apll" }; +PNAME(mux_gpll_cpll_dpll_p) = { "gpll", "dummy_cpll", "dummy_dpll" }; +PNAME(mux_gpll_cpll_p) = { "gpll", "dummy_cpll" }; +PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "dummy_cpll", "usb480m", "xin24m" }; +PNAME(mux_cpll_gpll_p) = { "dummy_cpll", "gpll" }; +PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "dummy_cpll", "xin24m" }; +PNAME(mux_cpll_hpll_gpll_p) = { "dummy_cpll", "dummy_hpll", "gpll" }; +PNAME(mux_cpll_gpll_hpll_p) = { "dummy_cpll", "gpll", "dummy_hpll" }; +PNAME(mux_gpll_cpll_hpll_p) = { "gpll", "dummy_cpll", "dummy_hpll" }; +PNAME(mux_gpll_cpll_apll_hpll_p) = { "gpll", "dummy_cpll", "dummy_apll", "dummy_hpll" }; +#endif + static u32 rgmii_mux_idx[] = { 2, 3, 0, 1 }; static struct rockchip_pll_clock rv1126_pmu_pll_clks[] __initdata = { [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, - 0, RV1126_PMU_PLL_CON(0), + CLK_IGNORE_UNUSED, RV1126_PMU_PLL_CON(0), RV1126_PMU_MODE, 0, 3, 0, rv1126_pll_rates), }; static struct rockchip_pll_clock rv1126_pll_clks[] __initdata = { [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, - 0, RV1126_PLL_CON(0), + CLK_IGNORE_UNUSED, RV1126_PLL_CON(0), RV1126_MODE_CON, 0, 0, 0, rv1126_pll_rates), [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, - 0, RV1126_PLL_CON(8), + CLK_IGNORE_UNUSED, RV1126_PLL_CON(8), RV1126_MODE_CON, 2, 1, 0, NULL), [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 0, RV1126_PLL_CON(16), @@ -420,7 +440,7 @@ static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = { MUX(CLK_MIPIDSIPHY_REF, "clk_mipidsiphy_ref", mux_mipidsiphy_ref_p, CLK_SET_RATE_PARENT, RV1126_PMU_CLKSEL_CON(7), 15, 1, MFLAGS), -#ifndef CONFIG_ROCKCHIP_THUNDER_BOOT +#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED, RV1126_PMU_CLKGATE_CON(0), 15, GFLAGS), @@ -1146,7 +1166,7 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = { GATE(PCLK_USBPHY_OTG, "pclk_usbphy_otg", "pclk_pdtop", 0, RV1126_CLKGATE_CON(19), 12, GFLAGS), -#ifndef CONFIG_ROCKCHIP_THUNDER_BOOT +#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE /* * Clock-Architecture Diagram 3 */ @@ -1354,8 +1374,10 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = { static const char *const rv1126_cru_critical_clocks[] __initconst = { "gpll", +#ifndef CONFIG_ROCKCHIP_LOW_PERFORMANCE "cpll", "hpll", +#endif "armclk", "pclk_dbg", "pclk_pdpmu", @@ -1367,11 +1389,15 @@ static const char *const rv1126_cru_critical_clocks[] __initconst = { "clk_ddrphy", "pclk_pdddr", "pclk_pdtop", +#if IS_ENABLED(CONFIG_USB_EHCI_HCD_PLATFORM) || IS_ENABLED(CONFIG_USB_OHCI_HCD_PLATFORM) "clk_usbhost_utmi_ohci", +#endif +#if IS_ENABLED(CONFIG_ROCKCHIP_MPP_VDPU2) || IS_ENABLED(CONFIG_ROCKCHIP_MPP_RKVDEC) "aclk_pdjpeg_niu", "hclk_pdjpeg_niu", "aclk_pdvdec_niu", "hclk_pdvdec_niu", +#endif }; static void __iomem *rv1126_cru_base;