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lcd: VPU: encl input buffer reset delay and limit input buffer din phase [1/1]

Browse Source 
PD#SWPL-6649

Problem:
encl input buffer reset delay and limit input buffer din phase

Solution:
set sync_vpp go filed back to encl_clk

Verify:
t962x3_ab301

Change-Id: I3fc681d408950e7647cfb08bb19bc66f2f8719b6
Signed-off-by: shaochan.liu <shaochan.liu@amlogic.com>
This commit is contained in:
shaochan.liu
2019-05-30 14:11:46 +08:00
committed by Tao Zeng
parent e9fd8597f4
commit 556ba87a2a
2 changed files with 10 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
View File

@@ -196,11 +196,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
/*[15:14]: 2'b10 or 2'b01*/
lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1));
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
break;
case LCD_CHIP_TM2:
/*[15:14]: 2'b10 or 2'b01 bit13:1*/
lcd_vcbus_write(ENCL_INBUF_CNTL1, (5 << 13) | (h_active - 1));
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
break;
default:
break;
}

6
drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
View File

@@ -181,11 +181,15 @@ static void lcd_venc_set(struct lcd_config_s *pconf)
switch (lcd_drv->data->chip_type) {
case LCD_CHIP_TL1:
case LCD_CHIP_TM2:
/*[15:14]: 2'b10 or 2'b01*/
lcd_vcbus_write(ENCL_INBUF_CNTL1, (2 << 14) | (h_active - 1));
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
break;
case LCD_CHIP_TM2:
/*[15:14]: 2'b10 or 2'b01, bit13:1*/
lcd_vcbus_write(ENCL_INBUF_CNTL1, (5 << 13) | (h_active - 1));
lcd_vcbus_write(ENCL_INBUF_CNTL0, 0x200);
break;
default:
break;
}